‘talos’ Dialect¶

Elaborated SystemVerilog semantic AST

The Talos dialect is the complete semantic landing boundary for the elaborated Slang frontend. Its concrete AST operations preserve source identity, resolved references, declared types, and the full elaborated hierarchy. Executable SSA, explicit scheduler effects, and flattened numeric descriptors belong to the separate simulation dialect.

Operations¶

`talos.assert.immediate` (::talos::ir::AssertImmediateOp)¶

Immediate assertion with explicit unknown handling

Syntax:

operation ::= `talos.assert.immediate` $severity $condition `,` $message attr-dict `:`
              qualified(type($condition))

Attributes:¶

Attribute	MLIR Type	Description
`severity`	::talos::ir::SeverityAttr	diagnostic severity
`message`	::mlir::StringAttr	string attribute

Operands:¶

Operand	Description
`condition`	one-bit exact four-state logic

`talos.assert.sample` (::talos::ir::AssertSampleOp)¶

Sample a concurrent assertion automaton

Syntax:

operation ::= `talos.assert.sample` $property `in` $region `(` $samples `)` attr-dict
              (`:` type($samples)^)?

Attributes:¶

Attribute	MLIR Type	Description
`property`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
`region`	::talos::ir::EventRegionAttr	IEEE 1800 event region

Operands:¶

Operand	Description
`samples`	variadic of any type

`talos.assoc.create` (::talos::ir::AssocCreateOp)¶

Allocate an associative array

Syntax:

operation ::= `talos.assoc.create` attr-dict `:` qualified(type($result))

Results:¶

Result	Description
`result`	associative array with reference semantics

`talos.assoc.delete` (::talos::ir::AssocDeleteOp)¶

Delete one key or clear an associative array

Syntax:

operation ::= `talos.assoc.delete` $array (`[` $key^ `]`)? attr-dict `:` functional-type(operands, results)

Operands:¶

Operand	Description
`array`	associative array with reference semantics
`key`	any type

`talos.assoc.element_ref` (::talos::ir::AssocElementRefOp)¶

Lookup or create an associative array element

Syntax:

operation ::= `talos.assoc.element_ref` $array `[` $key `]` attr-dict `:` functional-type(operands, results)

Operands:¶

Operand	Description
`array`	associative array with reference semantics
`key`	any type

Results:¶

Result	Description
`result`	mutable variable or object-field reference

`talos.assoc.exists` (::talos::ir::AssocExistsOp)¶

Test for an associative array key

Syntax:

operation ::= `talos.assoc.exists` $array `[` $key `]` attr-dict `:` qualified(type($array)) `,` type($key)

Operands:¶

Operand	Description
`array`	associative array with reference semantics
`key`	any type

Results:¶

Result	Description
`result`	1-bit signless integer

`talos.box` (::talos::ir::BoxOp)¶

Box a statically typed value

Syntax:

operation ::= `talos.box` $input attr-dict `:` type($input) `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`input`	any type

Results:¶

Result	Description
`result`	boxed runtime value for untyped containers and reflection

`talos.class` (::talos::ir::ClassOp)¶

Elaborated class descriptor

Syntax:

operation ::= `talos.class` $sym_name (`extends` $base^)? (`implements` $interfaces^)?
              attr-dict-with-keyword $body

Traits: IsolatedFromAbove, SymbolTable

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`sym_name`	::mlir::StringAttr	string attribute
`base`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
`interfaces`	::mlir::ArrayAttr	array attribute

`talos.class.end` (::talos::ir::ClassEndOp)¶

Terminate a class descriptor body

Syntax:

operation ::= `talos.class.end` attr-dict

Traits: Terminator

`talos.class.field` (::talos::ir::ClassFieldOp)¶

Class field layout entry

Syntax:

operation ::= `talos.class.field` $sym_name `at` $ordinal `:` $type attr-dict

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`sym_name`	::mlir::StringAttr	string attribute
`type`	::mlir::TypeAttr	any type attribute
`ordinal`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.class.method` (::talos::ir::ClassMethodOp)¶

Class method body and dispatch slot

Syntax:

operation ::= `talos.class.method` $sym_name `slot` $slot `virtual` `=` $isVirtual `:` $functionType
              attr-dict-with-keyword $body

Traits: IsolatedFromAbove

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`sym_name`	::mlir::StringAttr	string attribute
`functionType`	::mlir::TypeAttr	any type attribute
`slot`	::mlir::IntegerAttr	64-bit signless integer attribute
`isVirtual`	::mlir::BoolAttr	bool attribute

`talos.class.method_return` (::talos::ir::ClassMethodReturnOp)¶

Return from a class method

Syntax:

operation ::= `talos.class.method_return` ($values^ `:` type($values))? attr-dict

Traits: Terminator

Operands:¶

Operand	Description
`values`	variadic of any type

`talos.constraint.end` (::talos::ir::ConstraintEndOp)¶

Terminate a constraint graph

Syntax:

operation ::= `talos.constraint.end` attr-dict

Traits: Terminator

`talos.constraint.get` (::talos::ir::ConstraintGetOp)¶

Obtain a compiled constraint set

Syntax:

operation ::= `talos.constraint.get` $name attr-dict

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`name`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Results:¶

Result	Description
`result`	compiled random constraint graph handle

`talos.constraint.require` (::talos::ir::ConstraintRequireOp)¶

Require a symbolic predicate in a constraint graph

Syntax:

operation ::= `talos.constraint.require` $condition attr-dict

Operands:¶

Operand	Description
`condition`	1-bit signless integer

`talos.constraint.set` (::talos::ir::ConstraintSetOp)¶

Compiled constraint graph

Syntax:

operation ::= `talos.constraint.set` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`sym_name`	::mlir::StringAttr	string attribute

`talos.cover.sample` (::talos::ir::CoverSampleOp)¶

Sample functional or assertion coverage

Syntax:

operation ::= `talos.cover.sample` $coverpoint `(` $samples `)` attr-dict (`:` type($samples)^)?

Attributes:¶

Attribute	MLIR Type	Description
`coverpoint`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Operands:¶

Operand	Description
`samples`	variadic of any type

`talos.diagnostic` (::talos::ir::DiagnosticOp)¶

Emit a simulator diagnostic

Syntax:

operation ::= `talos.diagnostic` $severity $message `(` $arguments `)` attr-dict
              (`:` type($arguments)^)?

Attributes:¶

Attribute	MLIR Type	Description
`severity`	::talos::ir::SeverityAttr	diagnostic severity
`message`	::mlir::StringAttr	string attribute

Operands:¶

Operand	Description
`arguments`	variadic of any type

`talos.dpi.task_call` (::talos::ir::DPITaskCallOp)¶

Call a potentially time-consuming imported DPI task

Syntax:

operation ::= `talos.dpi.task_call` $callee `(` $arguments `)` attr-dict `:`
              functional-type($arguments, $results)

Pure/non-suspending DPI functions use the ordinary typed call path. This op exists for exported or context tasks which may interact with scheduler time and therefore cannot be modeled as an ordinary call.

Attributes:¶

Attribute	MLIR Type	Description
`callee`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Operands:¶

Operand	Description
`arguments`	variadic of any type

Results:¶

Result	Description
`results`	variadic of any type

`talos.dynarray.create` (::talos::ir::DynArrayCreateOp)¶

Allocate a dynamic array

Syntax:

operation ::= `talos.dynarray.create` $size (`default` $defaultValue^)? attr-dict `:`
              functional-type(operands, results)

Operands:¶

Operand	Description
`size`	64-bit signless integer
`defaultValue`	any type

Results:¶

Result	Description
`result`	dynamic array with reference semantics

`talos.dynarray.element_ref` (::talos::ir::DynArrayElementRefOp)¶

Bounds-checked dynamic array element reference

Syntax:

operation ::= `talos.dynarray.element_ref` $array `[` $index `]` attr-dict `:` functional-type(operands, results)

Operands:¶

Operand	Description
`array`	dynamic array with reference semantics
`index`	64-bit signless integer

Results:¶

Result	Description
`result`	mutable variable or object-field reference

`talos.dynarray.resize` (::talos::ir::DynArrayResizeOp)¶

Resize while preserving the required prefix

Syntax:

operation ::= `talos.dynarray.resize` $array `to` $size (`default` $defaultValue^)? attr-dict `:`
              functional-type(operands, results)

Operands:¶

Operand	Description
`array`	dynamic array with reference semantics
`size`	64-bit signless integer
`defaultValue`	any type

`talos.dynarray.size` (::talos::ir::DynArraySizeOp)¶

Read dynamic array size

Syntax:

operation ::= `talos.dynarray.size` $array attr-dict `:` qualified(type($array))

Operands:¶

Operand	Description
`array`	dynamic array with reference semantics

Results:¶

Result	Description
`result`	64-bit signless integer

`talos.event.create` (::talos::ir::EventCreateOp)¶

Create a named event object

Syntax:

operation ::= `talos.event.create` attr-dict

Results:¶

Result	Description
`event`	named event handle

`talos.event.trigger` (::talos::ir::EventTriggerOp)¶

Trigger a named event immediately or nonblockingly

Syntax:

operation ::= `talos.event.trigger` $event `in` $region `nonblocking` `=` $nonblocking attr-dict

Attributes:¶

Attribute	MLIR Type	Description
`region`	::talos::ir::EventRegionAttr	IEEE 1800 event region
`nonblocking`	::mlir::BoolAttr	bool attribute

Operands:¶

Operand	Description
`event`	named event handle

`talos.finish` (::talos::ir::FinishOp)¶

Request orderly simulation termination

Syntax:

operation ::= `talos.finish` $verbosity attr-dict

Attributes:¶

Attribute	MLIR Type	Description
`verbosity`	::mlir::IntegerAttr	32-bit signless integer attribute

`talos.force` (::talos::ir::ForceOp)¶

Override a variable or net until release

Syntax:

operation ::= `talos.force` $target `=` $value attr-dict `:` type($target) `,` type($value)

Operands:¶

Operand	Description
`target`	any type
`value`	any type

`talos.get_global` (::talos::ir::GetGlobalOp)¶

Obtain a reference to global storage

Syntax:

operation ::= `talos.get_global` $name attr-dict `:` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`name`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Results:¶

Result	Description
`result`	mutable variable or object-field reference

`talos.global` (::talos::ir::GlobalOp)¶

Design-lifetime mutable storage

Syntax:

operation ::= `talos.global` $sym_name `:` $type attr-dict-with-keyword $initializer

Traits: IsolatedFromAbove

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`sym_name`	::mlir::StringAttr	string attribute
`type`	::mlir::TypeAttr	any type attribute

`talos.global.return` (::talos::ir::GlobalReturnOp)¶

Return a global initializer value

Syntax:

operation ::= `talos.global.return` ($value^ `:` type($value))? attr-dict

Traits: Terminator

Operands:¶

Operand	Description
`value`	any type

`talos.load` (::talos::ir::LoadOp)¶

Read mutable variable or field storage

Syntax:

operation ::= `talos.load` $reference attr-dict `:` qualified(type($reference)) `->` type($result)

Operands:¶

Operand	Description
`reference`	mutable variable or object-field reference

Results:¶

Result	Description
`result`	any type

`talos.logic.binary` (::talos::ir::LogicBinaryOp)¶

IEEE four-state arithmetic, bitwise, or logical operation

Syntax:

operation ::= `talos.logic.binary` $kind $lhs `,` $rhs attr-dict `:` functional-type(operands, results)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`kind`	::talos::ir::LogicBinaryKindAttr	four-state binary operator

Operands:¶

Operand	Description
`lhs`	fixed-width exact four-state packed value
`rhs`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.bool_cast` (::talos::ir::LogicBoolCastOp)¶

SystemVerilog truth conversion preserving unknown

Syntax:

operation ::= `talos.logic.bool_cast` $input attr-dict `:` qualified(type($input)) `->`
              qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	one-bit exact four-state logic

`talos.logic.compare` (::talos::ir::LogicCompareOp)¶

Logical, case, wildcard, or relational comparison

Syntax:

operation ::= `talos.logic.compare` $kind $lhs `,` $rhs attr-dict `:` functional-type(operands, results)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`kind`	::talos::ir::LogicCompareKindAttr	four-state comparison operator

Operands:¶

Operand	Description
`lhs`	fixed-width exact four-state packed value
`rhs`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	any type

`talos.logic.concat` (::talos::ir::LogicConcatOp)¶

Packed concatenation preserving X and Z

Syntax:

operation ::= `talos.logic.concat` $inputs attr-dict `:` functional-type($inputs, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`inputs`	variadic of fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.constant` (::talos::ir::LogicConstantOp)¶

Exact four-state constant

Syntax:

operation ::= `talos.logic.constant` $value `,` $unknown attr-dict `:` qualified(type($result))

Creates !talos.logic<W> from two W-bit integer attributes. Unknown bits use value=0 for X and value=1 for Z. Known bits use value as the ordinary zero/one plane.

Traits: AlwaysSpeculatableImplTrait, ConstantLike

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`value`	::mlir::IntegerAttr	arbitrary integer attribute
`unknown`	::mlir::IntegerAttr	arbitrary integer attribute

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.dyn_extract` (::talos::ir::LogicDynExtractOp)¶

Dynamic packed part-select with SystemVerilog bounds behavior

Syntax:

operation ::= `talos.logic.dyn_extract` $input `from` $lowBit attr-dict `:` functional-type(operands, results)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value
`lowBit`	any type

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.extract` (::talos::ir::LogicExtractOp)¶

Constant packed part-select

Syntax:

operation ::= `talos.logic.extract` $input `from` $lowBit attr-dict `:` qualified(type($input)) `->`
              qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`lowBit`	::mlir::IntegerAttr	64-bit signless integer attribute

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.from_bits` (::talos::ir::LogicFromBitsOp)¶

Inject a two-state integer into exact four-state logic

Syntax:

operation ::= `talos.logic.from_bits` $input attr-dict `:` type($input) `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`input`	integer

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.insert` (::talos::ir::LogicInsertOp)¶

Constant packed part update

Syntax:

operation ::= `talos.logic.insert` $replacement `into` $input `at` $lowBit attr-dict `:`
              functional-type(operands, results)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`lowBit`	::mlir::IntegerAttr	64-bit signless integer attribute

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value
`replacement`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.is_known` (::talos::ir::LogicIsKnownOp)¶

Test whether every bit is zero or one

Syntax:

operation ::= `talos.logic.is_known` $input attr-dict `:` qualified(type($input)) `->` type($result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	1-bit signless integer

`talos.logic.mux` (::talos::ir::LogicMuxOp)¶

Conditional expression with IEEE unknown-condition merging

Syntax:

operation ::= `talos.logic.mux` $condition `?` $trueValue `:` $falseValue attr-dict `:`
              functional-type(operands, results)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`condition`	one-bit exact four-state logic
`trueValue`	fixed-width exact four-state packed value
`falseValue`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.reduce` (::talos::ir::LogicReduceOp)¶

Four-state reduction

Syntax:

operation ::= `talos.logic.reduce` $kind $input attr-dict `:` qualified(type($input)) `->`
              qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`kind`	::talos::ir::LogicReduceKindAttr	four-state reduction operator

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	one-bit exact four-state logic

`talos.logic.replicate` (::talos::ir::LogicReplicateOp)¶

Packed replication preserving X and Z

Syntax:

operation ::= `talos.logic.replicate` $input attr-dict `:` qualified(type($input)) `->`
              qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.resize` (::talos::ir::LogicResizeOp)¶

Truncate, zero-extend, or sign-extend four-state logic

Syntax:

operation ::= `talos.logic.resize` $input `signed` `=` $isSigned attr-dict `:` qualified(type($input)) `->`
              qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`isSigned`	::mlir::BoolAttr	bool attribute

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.shift` (::talos::ir::LogicShiftOp)¶

Four-state shift with independently typed shift amount

Syntax:

operation ::= `talos.logic.shift` $kind $input `by` $amount attr-dict `:`
              functional-type(operands, results)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`kind`	::talos::ir::LogicBinaryKindAttr	four-state binary operator

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value
`amount`	any type

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.logic.to_bits` (::talos::ir::LogicToBitsOp)¶

Apply SystemVerilog four-state to two-state conversion

Syntax:

operation ::= `talos.logic.to_bits` $input attr-dict `:` qualified(type($input)) `->` type($result)

Converts X and Z bits to zero as required when assigning a four-state value to a two-state packed type. This operation is deliberately explicit so an optimization cannot silently discard unknowns.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	integer

`talos.logic.unary` (::talos::ir::LogicUnaryOp)¶

IEEE four-state unary operation

Syntax:

operation ::= `talos.logic.unary` $kind $input attr-dict `:` qualified(type($input)) `->`
              qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`kind`	::talos::ir::LogicUnaryKindAttr	four-state unary operator

Operands:¶

Operand	Description
`input`	fixed-width exact four-state packed value

Results:¶

Result	Description
`result`	fixed-width exact four-state packed value

`talos.mailbox.create` (::talos::ir::MailboxCreateOp)¶

Create a bounded or unbounded mailbox

Syntax:

operation ::= `talos.mailbox.create` `bound` $bound attr-dict `:` qualified(type($result))

Attributes:¶

Attribute	MLIR Type	Description
`bound`	::mlir::IntegerAttr	64-bit signless integer attribute

Results:¶

Result	Description
`result`	typed or boxed blocking mailbox

`talos.mailbox.get` (::talos::ir::MailboxGetOp)¶

Blocking mailbox get

Syntax:

operation ::= `talos.mailbox.get` $mailbox attr-dict `:` qualified(type($mailbox)) `->` type($value)

Operands:¶

Operand	Description
`mailbox`	typed or boxed blocking mailbox

Results:¶

Result	Description
`value`	any type

`talos.mailbox.put` (::talos::ir::MailboxPutOp)¶

Blocking mailbox put

Syntax:

operation ::= `talos.mailbox.put` $value `into` $mailbox attr-dict `:` type($value) `,`
              qualified(type($mailbox))

Operands:¶

Operand	Description
`mailbox`	typed or boxed blocking mailbox
`value`	any type

`talos.mailbox.try_get` (::talos::ir::MailboxTryGetOp)¶

Nonblocking mailbox get

Syntax:

operation ::= `talos.mailbox.try_get` $mailbox attr-dict `:` functional-type(operands, results)

Operands:¶

Operand	Description
`mailbox`	typed or boxed blocking mailbox

Results:¶

Result	Description
`success`	1-bit signless integer
`value`	any type

`talos.nba.enqueue` (::talos::ir::NBAEnqueueOp)¶

Evaluate-now, update-later nonblocking assignment

Syntax:

operation ::= `talos.nba.enqueue` $value `to` $destination (`after` $delay^)? attr-dict `:`
              functional-type(operands, results)

Operands:¶

Operand	Description
`value`	any type
`destination`	mutable variable or object-field reference
`delay`	scaled simulation time

`talos.net.alloc` (::talos::ir::NetAllocOp)¶

Allocate a resolved net

Syntax:

operation ::= `talos.net.alloc` $kind attr-dict `:` qualified(type($result))

Attributes:¶

Attribute	MLIR Type	Description
`kind`	::talos::ir::NetKindAttr	net resolution function

Results:¶

Result	Description
`result`	resolved SystemVerilog net handle

`talos.net.concat` (::talos::ir::NetConcatOp)¶

Composite net lvalue formed by concatenation

Syntax:

operation ::= `talos.net.concat` $inputs attr-dict `:` functional-type($inputs, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`inputs`	variadic of resolved SystemVerilog net handle

Results:¶

Result	Description
`result`	resolved SystemVerilog net handle

`talos.net.drive` (::talos::ir::NetDriveOp)¶

Update one persistent driver of a resolved net

Syntax:

operation ::= `talos.net.drive` $net `[` $driver `]` `=` $value (`after` $delay^)?
              attr-dict `:` functional-type(operands, results)

Attributes:¶

Attribute	MLIR Type	Description
`driver`	::mlir::IntegerAttr	64-bit signless integer attribute

Operands:¶

Operand	Description
`net`	resolved SystemVerilog net handle
`value`	any type
`delay`	scaled simulation time

`talos.net.dyn_extract` (::talos::ir::NetDynExtractOp)¶

Net handle to a dynamically selected subelement

Syntax:

operation ::= `talos.net.dyn_extract` $input `from` $lowBit attr-dict `:`
              functional-type(operands, results)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`input`	resolved SystemVerilog net handle
`lowBit`	any type

Results:¶

Result	Description
`result`	resolved SystemVerilog net handle

`talos.net.extract` (::talos::ir::NetExtractOp)¶

Net handle to a constant subelement or part-select

Syntax:

operation ::= `talos.net.extract` $input `from` $lowBit attr-dict `:` qualified(type($input)) `->`
              qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`lowBit`	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:¶

Operand	Description
`input`	resolved SystemVerilog net handle

Results:¶

Result	Description
`result`	resolved SystemVerilog net handle

`talos.net.read` (::talos::ir::NetReadOp)¶

Read the currently resolved net value

Syntax:

operation ::= `talos.net.read` $net attr-dict `:` qualified(type($net)) `->` type($result)

Operands:¶

Operand	Description
`net`	resolved SystemVerilog net handle

Results:¶

Result	Description
`result`	any type

`talos.object.call` (::talos::ir::ObjectCallOp)¶

Call a dynamically dispatched class method

Syntax:

operation ::= `talos.object.call` $object `[` $method `]` `(` $arguments `)` attr-dict `:`
              functional-type(operands, results)

Attributes:¶

Attribute	MLIR Type	Description
`method`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Operands:¶

Operand	Description
`object`	nullable dynamically-dispatched class object handle
`arguments`	variadic of any type

Results:¶

Result	Description
`results`	variadic of any type

`talos.object.field_ref` (::talos::ir::ObjectFieldRefOp)¶

Obtain a mutable reference to an object field

Syntax:

operation ::= `talos.object.field_ref` $object `[` $field `]` attr-dict `:` qualified(type($result))

Attributes:¶

Attribute	MLIR Type	Description
`field`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Operands:¶

Operand	Description
`object`	nullable dynamically-dispatched class object handle

Results:¶

Result	Description
`result`	mutable variable or object-field reference

`talos.object.new` (::talos::ir::ObjectNewOp)¶

Allocate and construct a class object

Syntax:

operation ::= `talos.object.new` $className `(` $arguments `)` attr-dict `:`
              functional-type($arguments, $result)

Attributes:¶

Attribute	MLIR Type	Description
`className`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Operands:¶

Operand	Description
`arguments`	variadic of any type

Results:¶

Result	Description
`result`	nullable dynamically-dispatched class object handle

`talos.object.null` (::talos::ir::ObjectNullOp)¶

Null class handle

Syntax:

operation ::= `talos.object.null` attr-dict

Traits: AlwaysSpeculatableImplTrait, ConstantLike

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Results:¶

Result	Description
`result`	nullable dynamically-dispatched class object handle

`talos.object.release` (::talos::ir::ObjectReleaseOp)¶

Release a class object and run final ownership cleanup

Syntax:

operation ::= `talos.object.release` $object attr-dict

Operands:¶

Operand	Description
`object`	nullable dynamically-dispatched class object handle

`talos.object.retain` (::talos::ir::ObjectRetainOp)¶

Retain a class object across an ownership boundary

Syntax:

operation ::= `talos.object.retain` $object attr-dict

Operands:¶

Operand	Description
`object`	nullable dynamically-dispatched class object handle

`talos.process` (::talos::ir::ProcessOp)¶

Suspendable simulation process body

Syntax:

operation ::= `talos.process` $sym_name $kind `in` $entryRegion attr-dict-with-keyword $body

Traits: IsolatedFromAbove

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`sym_name`	::mlir::StringAttr	string attribute
`kind`	::talos::ir::ProcessKindAttr	simulation process kind
`entryRegion`	::talos::ir::EventRegionAttr	IEEE 1800 event region

`talos.process.join` (::talos::ir::ProcessJoinOp)¶

Wait according to join, join_any, or join_none semantics

Syntax:

operation ::= `talos.process.join` $kind $processes attr-dict (`:` qualified(type($processes))^)?

Attributes:¶

Attribute	MLIR Type	Description
`kind`	::talos::ir::JoinKindAttr	fork/join completion policy

Operands:¶

Operand	Description
`processes`	variadic of scheduler-owned process handle

`talos.process.kill` (::talos::ir::ProcessKillOp)¶

Disable or kill a process and its eligible descendants

Syntax:

operation ::= `talos.process.kill` $process attr-dict

Operands:¶

Operand	Description
`process`	scheduler-owned process handle

`talos.process.return` (::talos::ir::ProcessReturnOp)¶

Complete a process activation

Syntax:

operation ::= `talos.process.return` ($values^ `:` type($values))? attr-dict

Traits: Terminator

Operands:¶

Operand	Description
`values`	variadic of any type

`talos.process.spawn` (::talos::ir::ProcessSpawnOp)¶

Create and enqueue a child process

Syntax:

operation ::= `talos.process.spawn` $callee `(` $captures `)` `in` $region attr-dict `:`
              functional-type($captures, $process)

Attributes:¶

Attribute	MLIR Type	Description
`callee`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
`region`	::talos::ir::EventRegionAttr	IEEE 1800 event region

Operands:¶

Operand	Description
`captures`	variadic of any type

Results:¶

Result	Description
`process`	scheduler-owned process handle

`talos.randc.create` (::talos::ir::RandCCreateOp)¶

Create a random-cyclic state machine

Syntax:

operation ::= `talos.randc.create` $stream attr-dict `:` qualified(type($result))

Operands:¶

Operand	Description
`stream`	deterministic hierarchical pseudorandom stream

Results:¶

Result	Description
`result`	state for a random-cyclic variable

`talos.randc.next` (::talos::ir::RandCNextOp)¶

Produce the next nonrepeating value in a randc cycle

Syntax:

operation ::= `talos.randc.next` $state attr-dict `:` qualified(type($state)) `->` type($result)

Operands:¶

Operand	Description
`state`	state for a random-cyclic variable

Results:¶

Result	Description
`result`	any type

`talos.random.next` (::talos::ir::RandomNextOp)¶

Draw unbiased random bits from a stream

Syntax:

operation ::= `talos.random.next` $stream attr-dict `:` type($result)

Operands:¶

Operand	Description
`stream`	deterministic hierarchical pseudorandom stream

Results:¶

Result	Description
`result`	integer

`talos.random.restore` (::talos::ir::RandomRestoreOp)¶

Restore random stream state for set_randstate

Syntax:

operation ::= `talos.random.restore` $stream `from` $state attr-dict

Operands:¶

Operand	Description
`stream`	deterministic hierarchical pseudorandom stream
`state`	saved random stream state

`talos.random.save` (::talos::ir::RandomSaveOp)¶

Snapshot random stream state for get_randstate

Syntax:

operation ::= `talos.random.save` $stream attr-dict

Operands:¶

Operand	Description
`stream`	deterministic hierarchical pseudorandom stream

Results:¶

Result	Description
`result`	saved random stream state

`talos.random.stream_create` (::talos::ir::RandomStreamCreateOp)¶

Create a deterministic stream from an explicit seed

Syntax:

operation ::= `talos.random.stream_create` $seed attr-dict

Operands:¶

Operand	Description
`seed`	64-bit signless integer

Results:¶

Result	Description
`result`	deterministic hierarchical pseudorandom stream

`talos.random.stream_split` (::talos::ir::RandomStreamSplitOp)¶

Derive a deterministic child stream

Syntax:

operation ::= `talos.random.stream_split` $parent `by` $streamId attr-dict

Operands:¶

Operand	Description
`parent`	deterministic hierarchical pseudorandom stream
`streamId`	64-bit signless integer

Results:¶

Result	Description
`result`	deterministic hierarchical pseudorandom stream

`talos.randomize` (::talos::ir::RandomizeOp)¶

Solve constraints and commit random variables atomically

Syntax:

operation ::= `talos.randomize` $object `using` $stream `with` $constraints attr-dict

Operands:¶

Operand	Description
`object`	nullable dynamically-dispatched class object handle
`stream`	deterministic hierarchical pseudorandom stream
`constraints`	compiled random constraint graph handle

Results:¶

Result	Description
`success`	1-bit signless integer

`talos.ref.concat` (::talos::ir::RefConcatOp)¶

Composite lvalue reference formed by concatenation

Syntax:

operation ::= `talos.ref.concat` $inputs attr-dict `:` functional-type($inputs, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`inputs`	variadic of mutable variable or object-field reference

Results:¶

Result	Description
`result`	mutable variable or object-field reference

`talos.ref.dyn_extract` (::talos::ir::RefDynExtractOp)¶

Reference to a dynamically selected subelement

Syntax:

operation ::= `talos.ref.dyn_extract` $input `from` $lowBit attr-dict `:`
              functional-type(operands, results)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`input`	mutable variable or object-field reference
`lowBit`	any type

Results:¶

Result	Description
`result`	mutable variable or object-field reference

`talos.ref.extract` (::talos::ir::RefExtractOp)¶

Reference to a constant subelement or part-select

Syntax:

operation ::= `talos.ref.extract` $input `from` $lowBit attr-dict `:` qualified(type($input)) `->`
              qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`lowBit`	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:¶

Operand	Description
`input`	mutable variable or object-field reference

Results:¶

Result	Description
`result`	mutable variable or object-field reference

`talos.region.enqueue` (::talos::ir::RegionEnqueueOp)¶

Enqueue a process into an explicit IEEE event region

Syntax:

operation ::= `talos.region.enqueue` $process `in` $region (`after` $delay^)? attr-dict

Attributes:¶

Attribute	MLIR Type	Description
`region`	::talos::ir::EventRegionAttr	IEEE 1800 event region

Operands:¶

Operand	Description
`process`	scheduler-owned process handle
`delay`	scaled simulation time

`talos.release` (::talos::ir::ReleaseOp)¶

Remove a force and restore ordinary update behavior

Syntax:

operation ::= `talos.release` $target attr-dict `:` type($target)

Operands:¶

Operand	Description
`target`	any type

`talos.semaphore.create` (::talos::ir::SemaphoreCreateOp)¶

Create a semaphore with an initial key count

Syntax:

operation ::= `talos.semaphore.create` $keys attr-dict

Operands:¶

Operand	Description
`keys`	64-bit signless integer

Results:¶

Result	Description
`result`	SystemVerilog semaphore handle

`talos.semaphore.get` (::talos::ir::SemaphoreGetOp)¶

Blocking semaphore key acquisition

Syntax:

operation ::= `talos.semaphore.get` $keys `from` $semaphore attr-dict

Operands:¶

Operand	Description
`semaphore`	SystemVerilog semaphore handle
`keys`	64-bit signless integer

`talos.semaphore.put` (::talos::ir::SemaphorePutOp)¶

Return semaphore keys

Syntax:

operation ::= `talos.semaphore.put` $keys `to` $semaphore attr-dict

Operands:¶

Operand	Description
`semaphore`	SystemVerilog semaphore handle
`keys`	64-bit signless integer

`talos.semaphore.try_get` (::talos::ir::SemaphoreTryGetOp)¶

Nonblocking semaphore key acquisition

Syntax:

operation ::= `talos.semaphore.try_get` $keys `from` $semaphore attr-dict

Operands:¶

Operand	Description
`semaphore`	SystemVerilog semaphore handle
`keys`	64-bit signless integer

Results:¶

Result	Description
`success`	1-bit signless integer

`talos.stop` (::talos::ir::StopOp)¶

Request interactive simulation suspension

Syntax:

operation ::= `talos.stop` $verbosity attr-dict

Attributes:¶

Attribute	MLIR Type	Description
`verbosity`	::mlir::IntegerAttr	32-bit signless integer attribute

`talos.store` (::talos::ir::StoreOp)¶

Blocking update of mutable variable or field storage

Syntax:

operation ::= `talos.store` $value `to` $reference attr-dict `:` type($value) `,`
              qualified(type($reference))

Operands:¶

Operand	Description
`value`	any type
`reference`	mutable variable or object-field reference

`talos.suspend.condition` (::talos::ir::SuspendConditionOp)¶

Suspend until a wait expression becomes true

Syntax:

operation ::= `talos.suspend.condition` $condition `resume` $resumeRegion attr-dict `:`
              qualified(type($condition))

Attributes:¶

Attribute	MLIR Type	Description
`resumeRegion`	::talos::ir::EventRegionAttr	IEEE 1800 event region

Operands:¶

Operand	Description
`condition`	one-bit exact four-state logic

`talos.suspend.delay` (::talos::ir::SuspendDelayOp)¶

Suspend the current process for simulation time

Syntax:

operation ::= `talos.suspend.delay` $delay `resume` $resumeRegion attr-dict

Attributes:¶

Attribute	MLIR Type	Description
`resumeRegion`	::talos::ir::EventRegionAttr	IEEE 1800 event region

Operands:¶

Operand	Description
`delay`	scaled simulation time

`talos.suspend.edge` (::talos::ir::SuspendEdgeOp)¶

Suspend until an IEEE four-state edge transition

Syntax:

operation ::= `talos.suspend.edge` $edge $observed `resume` $resumeRegion attr-dict `:`
              qualified(type($observed))

Attributes:¶

Attribute	MLIR Type	Description
`edge`	::talos::ir::EdgeKindAttr	SystemVerilog event edge
`resumeRegion`	::talos::ir::EventRegionAttr	IEEE 1800 event region

Operands:¶

Operand	Description
`observed`	mutable variable or object-field reference

`talos.suspend.event` (::talos::ir::SuspendEventOp)¶

Suspend until a named event is triggered

Syntax:

operation ::= `talos.suspend.event` $event `resume` $resumeRegion attr-dict

Attributes:¶

Attribute	MLIR Type	Description
`resumeRegion`	::talos::ir::EventRegionAttr	IEEE 1800 event region

Operands:¶

Operand	Description
`event`	named event handle

`talos.sv.assertion.abort` (::talos::ir::SVAbortAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.abort` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`action`	::talos::ir::SVAssertionAbortActionAttr	accept or reject property abort action
`is_synchronous`	::mlir::BoolAttr	bool attribute

`talos.sv.assertion.binary` (::talos::ir::SVBinaryAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.binary` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`operator_kind`	::talos::ir::SVAssertionBinaryOperatorAttr	SystemVerilog binary sequence or property operator
`operator_range`	::mlir::TypeAttr	any type attribute

`talos.sv.assertion.case` (::talos::ir::SVCaseAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.case` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`item_group_sizes`	::mlir::ArrayAttr	array attribute
`has_default`	::mlir::BoolAttr	bool attribute

`talos.sv.assertion.clocking` (::talos::ir::SVClockingAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.clocking` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.assertion.conditional` (::talos::ir::SVConditionalAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.conditional` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`has_else`	::mlir::BoolAttr	bool attribute

`talos.sv.assertion.disable_iff` (::talos::ir::SVDisableIffAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.disable_iff` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.assertion.first_match` (::talos::ir::SVFirstMatchAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.first_match` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`match_item_count`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.assertion.invalid` (::talos::ir::SVInvalidAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.invalid` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosRejectInvalidSemanticNode, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.assertion.sequence_concat` (::talos::ir::SVSequenceConcatExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.sequence_concat` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`delays`	::mlir::ArrayAttr	Array of dictionary attributes

`talos.sv.assertion.sequence_with_match` (::talos::ir::SVSequenceWithMatchExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.sequence_with_match` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyRepetitionMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`match_item_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`has_repetition`	::mlir::BoolAttr	bool attribute
`repetition_kind`	::talos::ir::SVSequenceRepetitionKindAttr	SystemVerilog sequence repetition kind
`repetition_min`	::mlir::IntegerAttr	64-bit signless integer attribute
`repetition_max`	::mlir::IntegerAttr	64-bit signless integer attribute
`repetition_is_unbounded`	::mlir::BoolAttr	bool attribute

`talos.sv.assertion.simple` (::talos::ir::SVSimpleAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.simple` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyRepetitionMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_null`	::mlir::BoolAttr	bool attribute
`has_repetition`	::mlir::BoolAttr	bool attribute
`repetition_kind`	::talos::ir::SVSequenceRepetitionKindAttr	SystemVerilog sequence repetition kind
`repetition_min`	::mlir::IntegerAttr	64-bit signless integer attribute
`repetition_max`	::mlir::IntegerAttr	64-bit signless integer attribute
`repetition_is_unbounded`	::mlir::BoolAttr	bool attribute

`talos.sv.assertion.strong_weak` (::talos::ir::SVStrongWeakAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.strong_weak` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`strength`	::talos::ir::SVAssertionStrengthAttr	strong or weak property qualification

`talos.sv.assertion.unary` (::talos::ir::SVUnaryAssertionExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.assertion.unary` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifySequenceRangeMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`operator_kind`	::talos::ir::SVAssertionUnaryOperatorAttr	SystemVerilog unary sequence or property operator
`has_range`	::mlir::BoolAttr	bool attribute
`range_min`	::mlir::IntegerAttr	64-bit signless integer attribute
`range_max`	::mlir::IntegerAttr	64-bit signless integer attribute
`range_is_unbounded`	::mlir::BoolAttr	bool attribute

`talos.sv.bins.binary` (::talos::ir::SVBinaryBinsSelectExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.bins.binary` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageSelectorNode, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyCoverageBinarySelectorMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`enclosing_cross_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`operator_kind`	::talos::ir::SVCoverageSelectBinaryOperatorAttr	binary coverage-bin selection operator

`talos.sv.bins.condition` (::talos::ir::SVConditionBinsSelectExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.bins.condition` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageSelectorNode, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyCoverageConditionSelectorMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`enclosing_cross_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`target_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`intersect_count`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.bins.cross_id` (::talos::ir::SVCrossIdBinsSelectExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.bins.cross_id` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageSelectorNode, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyCoverageCrossIdSelectorMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`enclosing_cross_symbol`	::mlir::SymbolRefAttr	symbol reference attribute

`talos.sv.bins.invalid` (::talos::ir::SVInvalidBinsSelectExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.bins.invalid` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosRejectInvalidSemanticNode, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.bins.set_expr` (::talos::ir::SVSetExprBinsSelectExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.bins.set_expr` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageSelectorNode, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyCoverageSetSelectorMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`enclosing_cross_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`has_matches`	::mlir::BoolAttr	bool attribute

`talos.sv.bins.unary` (::talos::ir::SVUnaryBinsSelectExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.bins.unary` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageSelectorNode, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyCoverageUnarySelectorMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`enclosing_cross_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`operator_kind`	::talos::ir::SVCoverageSelectUnaryOperatorAttr	unary coverage-bin selection operator

`talos.sv.bins.with_filter` (::talos::ir::SVBinSelectWithFilterExprOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.bins.with_filter` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageSelectorNode, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyCoverageWithSelectorMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`enclosing_cross_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`has_matches`	::mlir::BoolAttr	bool attribute

`talos.sv.constraint.conditional` (::talos::ir::SVConditionalConstraintOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.constraint.conditional` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`has_else`	::mlir::BoolAttr	bool attribute

`talos.sv.constraint.disable_soft` (::talos::ir::SVDisableSoftConstraintOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.constraint.disable_soft` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.constraint.expression` (::talos::ir::SVExpressionConstraintOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.constraint.expression` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`is_soft`	::mlir::BoolAttr	bool attribute

`talos.sv.constraint.foreach` (::talos::ir::SVForeachConstraintOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.constraint.foreach` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`loop_dimensions`	::mlir::ArrayAttr	Array of dictionary attributes

`talos.sv.constraint.implication` (::talos::ir::SVImplicationConstraintOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.constraint.implication` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.constraint.invalid` (::talos::ir::SVInvalidConstraintOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.constraint.invalid` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosRejectInvalidSemanticNode, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.constraint.list` (::talos::ir::SVConstraintListOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.constraint.list` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`item_count`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.constraint.solve_before` (::talos::ir::SVSolveBeforeConstraintOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.constraint.solve_before` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`solve_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`after_count`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.constraint.uniqueness` (::talos::ir::SVUniquenessConstraintOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.constraint.uniqueness` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`item_count`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.coverage.option` (::talos::ir::SVCoverageOptionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.coverage.option` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageOptionNode, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyCoverageOptionMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`owner_kind`	::talos::ir::SVCoverageOptionOwnerKindAttr	coverage construct that owns a definition-time option setter
`scope_kind`	::talos::ir::SVCoverageOptionScopeKindAttr	instance option or covergroup type option
`option_kind`	::talos::ir::SVCoverageOptionKindAttr	standard coverage option identity
`owner_symbol`	::mlir::SymbolRefAttr	symbol reference attribute

`talos.sv.expression.arbitrary_symbol` (::talos::ir::SVArbitrarySymbolExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.arbitrary_symbol` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute

`talos.sv.expression.assertion_instance` (::talos::ir::SVAssertionInstanceExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.assertion_instance` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode, TalosVerifyAssertionInvocationMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute
`argument_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`argument_formal_symbols`	::mlir::ArrayAttr	symbol ref array attribute
`argument_formal_paths`	::mlir::ArrayAttr	string array attribute
`argument_kinds`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`local_variable_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`local_variable_symbols`	::mlir::ArrayAttr	symbol ref array attribute
`local_variable_paths`	::mlir::ArrayAttr	string array attribute
`local_variable_has_initializer`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`is_recursive_property`	::mlir::BoolAttr	bool attribute
`has_expanded_body`	::mlir::BoolAttr	bool attribute

`talos.sv.expression.assignment` (::talos::ir::SVAssignmentExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.assignment` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`assignment_kind`	::talos::ir::SVAssignmentKindAttr	SystemVerilog assignment scheduling kind
`has_timing_control`	::mlir::BoolAttr	bool attribute
`operator_kind`	::talos::ir::SVBinaryOperatorAttr	complete source-level SystemVerilog binary operator

`talos.sv.expression.binary_op` (::talos::ir::SVBinaryExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.binary_op` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`operator_kind`	::talos::ir::SVBinaryOperatorAttr	complete source-level SystemVerilog binary operator

`talos.sv.expression.call` (::talos::ir::SVCallExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.call` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`callee_name`	::mlir::StringAttr	string attribute
`is_system_call`	::mlir::BoolAttr	bool attribute
`is_builtin_method`	::mlir::UnitAttr	unit attribute
`subroutine_kind`	::talos::ir::SVSubroutineKindAttr	SystemVerilog function or task kind
`argument_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`has_this_class`	::mlir::BoolAttr	bool attribute
`is_super_class`	::mlir::BoolAttr	bool attribute
`has_output_arguments`	::mlir::BoolAttr	bool attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute
`system_scope_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`system_scope_path`	::mlir::StringAttr	string attribute
`system_library_cell`	::mlir::StringAttr	string attribute
`iterator_variable_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`iterator_variable_path`	::mlir::StringAttr	string attribute
`has_iterator_expression`	::mlir::BoolAttr	bool attribute
`has_inline_constraints`	::mlir::BoolAttr	bool attribute
`constraint_restrictions`	::mlir::ArrayAttr	array attribute
`defaulted_arguments`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`dynamic_cast_kind`	::talos::ir::SVDynamicCastKindAttr	Elaborated SystemVerilog dynamic-cast behavior
`dynamic_cast_enum_values`	::mlir::ArrayAttr	string array attribute
`enum_method_values`	::mlir::ArrayAttr	string array attribute
`enum_method_names`	::mlir::ArrayAttr	string array attribute
`typename_spelling`	::mlir::StringAttr	string attribute
`readmem_enum_key_values`	::mlir::ArrayAttr	string array attribute
`readmem_enum_element_values`	::mlir::ArrayAttr	string array attribute
`is_void_casted`	::mlir::UnitAttr	unit attribute

`talos.sv.expression.clocking_event` (::talos::ir::SVClockingEventExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.clocking_event` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.concatenation` (::talos::ir::SVConcatenationExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.concatenation` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.conditional_op` (::talos::ir::SVConditionalExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.conditional_op` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`condition_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`condition_pattern_flags`	::mlir::DenseI64ArrayAttr	i64 dense array attribute

`talos.sv.expression.conversion` (::talos::ir::SVConversionExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.conversion` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.copy_class` (::talos::ir::SVCopyClassExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.copy_class` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.data_type` (::talos::ir::SVDataTypeExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.data_type` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.dist` (::talos::ir::SVDistExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.dist` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`item_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`item_has_weight`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`item_weight_kinds`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`has_default_weight`	::mlir::BoolAttr	bool attribute
`default_weight_kind`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.expression.element_select` (::talos::ir::SVElementSelectExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.element_select` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.empty_argument` (::talos::ir::SVEmptyArgumentExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.empty_argument` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.hierarchical_value` (::talos::ir::SVHierarchicalValueExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.hierarchical_value` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute

`talos.sv.expression.inside` (::talos::ir::SVInsideExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.inside` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`item_count`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.expression.integer_literal` (::talos::ir::SVIntegerLiteralOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.integer_literal` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`constant_value`	::mlir::StringAttr	string attribute
`is_declared_unsized`	::mlir::BoolAttr	bool attribute

`talos.sv.expression.l_value_reference` (::talos::ir::SVLValueReferenceExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.l_value_reference` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.member_access` (::talos::ir::SVMemberAccessExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.member_access` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute

`talos.sv.expression.min_typ_max` (::talos::ir::SVMinTypMaxExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.min_typ_max` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.named_value` (::talos::ir::SVNamedValueExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.named_value` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute

`talos.sv.expression.new_array` (::talos::ir::SVNewArrayExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.new_array` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.new_class` (::talos::ir::SVNewClassExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.new_class` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_super_class`	::mlir::BoolAttr	bool attribute

`talos.sv.expression.new_covergroup` (::talos::ir::SVNewCovergroupExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.new_covergroup` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`argument_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`defaulted_arguments`	::mlir::DenseI64ArrayAttr	i64 dense array attribute

`talos.sv.expression.null_literal` (::talos::ir::SVNullLiteralOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.null_literal` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.range_select` (::talos::ir::SVRangeSelectExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.range_select` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`selection_kind`	::talos::ir::SVRangeSelectionKindAttr	SystemVerilog packed range selection kind

`talos.sv.expression.real_literal` (::talos::ir::SVRealLiteralOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.real_literal` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`constant_value`	::mlir::StringAttr	string attribute
`is_declared_unsized`	::mlir::BoolAttr	bool attribute

`talos.sv.expression.replicated_assignment_pattern` (::talos::ir::SVReplicatedAssignmentPatternExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.replicated_assignment_pattern` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.replication` (::talos::ir::SVReplicationExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.replication` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.simple_assignment_pattern` (::talos::ir::SVSimpleAssignmentPatternExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.simple_assignment_pattern` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.streaming` (::talos::ir::SVStreamingConcatenationExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.streaming` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`slice_size`	::mlir::IntegerAttr	64-bit signless integer attribute
`bitstream_width`	::mlir::IntegerAttr	64-bit signless integer attribute
`stream_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`stream_with_flags`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`is_fixed_size`	::mlir::BoolAttr	bool attribute

`talos.sv.expression.string_literal` (::talos::ir::SVStringLiteralOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.string_literal` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`constant_value`	::mlir::StringAttr	string attribute
`is_declared_unsized`	::mlir::BoolAttr	bool attribute

`talos.sv.expression.structured_assignment_pattern` (::talos::ir::SVStructuredAssignmentPatternExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.structured_assignment_pattern` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`member_setter_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`member_setter_ordinals`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`type_setter_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`type_setter_types`	::mlir::ArrayAttr	type array attribute
`index_setter_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`has_default_setter`	::mlir::BoolAttr	bool attribute

`talos.sv.expression.tagged_union` (::talos::ir::SVTaggedUnionExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.tagged_union` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.time_literal` (::talos::ir::SVTimeLiteralOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.time_literal` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`constant_value`	::mlir::StringAttr	string attribute
`time_scale`	::mlir::StringAttr	string attribute

`talos.sv.expression.type_reference` (::talos::ir::SVTypeReferenceExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.type_reference` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.unary_op` (::talos::ir::SVUnaryExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.unary_op` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`operator_kind`	::talos::ir::SVUnaryOperatorAttr	complete source-level SystemVerilog unary operator

`talos.sv.expression.unbased_unsized_integer_literal` (::talos::ir::SVUnbasedUnsizedIntegerLiteralOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.unbased_unsized_integer_literal` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`constant_value`	::mlir::StringAttr	string attribute
`is_declared_unsized`	::mlir::BoolAttr	bool attribute

`talos.sv.expression.unbounded_literal` (::talos::ir::SVUnboundedLiteralOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.unbounded_literal` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.expression.value_range` (::talos::ir::SVValueRangeExpressionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.expression.value_range` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticExpressionNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`range_kind`	::talos::ir::SVValueRangeKindAttr	kind of membership value range

`talos.sv.pattern.constant` (::talos::ir::SVConstantPatternOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.pattern.constant` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.pattern.invalid` (::talos::ir::SVInvalidPatternOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.pattern.invalid` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosRejectInvalidSemanticNode, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.pattern.structure` (::talos::ir::SVStructurePatternOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.pattern.structure` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`field_ordinals`	::mlir::DenseI64ArrayAttr	i64 dense array attribute

`talos.sv.pattern.tagged` (::talos::ir::SVTaggedPatternOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.pattern.tagged` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosTaggedPatternNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute
`field_ordinal`	::mlir::IntegerAttr	64-bit signless integer attribute
`packed_offset`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.pattern.variable` (::talos::ir::SVVariablePatternOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.pattern.variable` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosPatternVariableNode, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute
`field_ordinal`	::mlir::IntegerAttr	64-bit signless integer attribute
`packed_offset`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.pattern.wildcard` (::talos::ir::SVWildcardPatternOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.pattern.wildcard` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.port.connection` (::talos::ir::SVPortConnectionOp)¶

One resolved scalar elaborated port connection

Syntax:

operation ::= `talos.sv.port.connection` attr-dict-with-keyword $internal $actual

Traits: NoTerminator, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`formal_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`formal_path`	::mlir::StringAttr	string attribute
`formal_ordinal`	::mlir::IntegerAttr	64-bit signless integer attribute
`formal_name`	::mlir::StringAttr	string attribute
`direction`	::talos::ir::SVArgumentDirectionAttr	SystemVerilog port or argument direction
`formal_type`	::mlir::TypeAttr	any type attribute
`is_net`	::mlir::BoolAttr	bool attribute
`is_ansi`	::mlir::BoolAttr	bool attribute
`actual_is_constant`	::mlir::BoolAttr	bool attribute
`unconnected_drive_value`	::mlir::BoolAttr	bool attribute
`provenance`	::talos::ir::SVPortConnectionKindAttr	elaborated port association provenance
`internal_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`internal_path`	::mlir::StringAttr	string attribute
`interface_instance_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`interface_instance_path`	::mlir::StringAttr	string attribute
`interface_shape`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`selected_modport`	::mlir::StringAttr	string attribute
`drive_strength0`	::talos::ir::SVDriveStrengthAttr	SystemVerilog drive strength for one logic polarity
`drive_strength1`	::talos::ir::SVDriveStrengthAttr	SystemVerilog drive strength for one logic polarity
`unsupported_delay`	::mlir::StringAttr	string attribute

`talos.sv.rand_seq.case` (::talos::ir::SVCaseProdOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.rand_seq.case` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.rand_seq.code_block` (::talos::ir::SVCodeBlockProdOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.rand_seq.code_block` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.rand_seq.frozen_production` (::talos::ir::SVFrozenRandSeqProductionOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.rand_seq.frozen_production` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute
`argument_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`rule_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`rule_item_counts`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`rule_has_weights`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`rule_has_weight_code_blocks`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`rule_is_rand_join`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`rule_has_rand_join_expressions`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`formal_arguments`	::mlir::ArrayAttr	array attribute
`rule_variables`	::mlir::ArrayAttr	array attribute

`talos.sv.rand_seq.if_else` (::talos::ir::SVIfElseProdOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.rand_seq.if_else` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.rand_seq.item` (::talos::ir::SVProdItemOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.rand_seq.item` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.rand_seq.repeat` (::talos::ir::SVRepeatProdOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.rand_seq.repeat` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.source.binary_expression` (::talos::ir::SVSourceBinaryExpressionOp)¶

Unbound binary operation in an original default

Syntax:

operation ::= `talos.sv.source.binary_expression` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`operator_kind`	::talos::ir::SVBinaryOperatorAttr	complete source-level SystemVerilog binary operator

`talos.sv.source.class_constraint` (::talos::ir::SVSourceClassConstraintSymbolOp)¶

Lexical normal constraint without a bound constraint body

Syntax:

operation ::= `talos.sv.source.class_constraint` $sym_name attr-dict-with-keyword $body

Owned by a lexical class definition, with an empty body and no semantic_type. The source position is the declaration or prototype position. has_external_definition records an exact out-of-block definition lookup without binding its constraint expressions.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_static`	::mlir::UnitAttr	unit attribute
`is_pure`	::mlir::UnitAttr	unit attribute
`is_prototype`	::mlir::UnitAttr	unit attribute
`has_external_definition`	::mlir::BoolAttr	bool attribute

`talos.sv.source.class_definition` (::talos::ir::SVSourceClassDefinitionSymbolOp)¶

Lexical nested class declaration without a specialization

Syntax:

operation ::= `talos.sv.source.class_definition` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_abstract`	::mlir::BoolAttr	bool attribute
`is_interface`	::mlir::BoolAttr	bool attribute
`is_final`	::mlir::BoolAttr	bool attribute
`is_parameterized`	::mlir::BoolAttr	bool attribute

`talos.sv.source.class_extends` (::talos::ir::SVSourceClassExtendsOp)¶

Lexical class inheritance without choosing a specialization

Syntax:

operation ::= `talos.sv.source.class_extends` attr-dict-with-keyword $body

The base declaration is an exact source class symbol. An unresolved dependent base instead retains its source spelling in unavailable_base; exactly one representation is required. Explicit parameter and constructor argument syntax is retained separately until its source expression graph can be represented. An absent list is distinct from an unavailable one. The node has no effective type or elaborated body.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: SymbolUserOpInterface

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`base_definition`	::mlir::SymbolRefAttr	symbol reference attribute
`unavailable_base`	::mlir::StringAttr	string attribute
`parameter_arguments`	::mlir::StringAttr	string attribute
`constructor_arguments`	::mlir::StringAttr	string attribute

`talos.sv.source.class_method` (::talos::ir::SVSourceClassMethodSymbolOp)¶

Lexical generic-class method without an effective signature

Syntax:

operation ::= `talos.sv.source.class_method` $sym_name attr-dict-with-keyword $body

Owned by a lexical class definition, with an empty body and no semantic_type. The symbol preserves declaration identity and source-only modifiers; it does not designate a specialized executable method.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`subroutine_kind`	::talos::ir::SVSubroutineKindAttr	SystemVerilog function or task kind
`default_lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`member_visibility`	::talos::ir::SVVisibilityAttr	SystemVerilog class member visibility
`is_static`	::mlir::UnitAttr	unit attribute
`is_declared_virtual`	::mlir::UnitAttr	unit attribute
`is_pure`	::mlir::UnitAttr	unit attribute
`is_constructor`	::mlir::UnitAttr	unit attribute
`is_extern`	::mlir::UnitAttr	unit attribute
`source_virtuality`	::mlir::BoolAttr	bool attribute

`talos.sv.source.class_parameter_actual` (::talos::ir::SVSourceClassParameterActualOp)¶

An exact lexical class parameter connection

Syntax:

operation ::= `talos.sv.source.class_parameter_actual` attr-dict-with-keyword $body

The parameter is the exact nonlocal declaration of the referenced base. A supported explicit value or type is its single child. A named empty connection carries use_default and no child, preserving the original declaration default. An unsupported expression retains unavailable_rhs instead, without an effective value or type.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: SymbolUserOpInterface

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`parameter`	::mlir::SymbolRefAttr	symbol reference attribute
`is_named`	::mlir::UnitAttr	unit attribute
`use_default`	::mlir::UnitAttr	unit attribute
`unavailable_rhs`	::mlir::StringAttr	string attribute

`talos.sv.source.class_property` (::talos::ir::SVSourceClassPropertySymbolOp)¶

Lexical generic class property without executable storage

Syntax:

operation ::= `talos.sv.source.class_property` $sym_name attr-dict-with-keyword $body

Owns exactly one source declared-type node. The declaration preserves its lexical identity and modifiers without binding a specialization or initializer.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`member_visibility`	::talos::ir::SVVisibilityAttr	SystemVerilog class member visibility
`rand_mode`	::talos::ir::SVRandModeAttr	SystemVerilog randomization mode
`is_const`	::mlir::UnitAttr	unit attribute

`talos.sv.source.class_type_alias` (::talos::ir::SVSourceClassTypeAliasSymbolOp)¶

Lexical generic class typedef without an effective target

Syntax:

operation ::= `talos.sv.source.class_type_alias` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`member_visibility`	::talos::ir::SVVisibilityAttr	SystemVerilog class member visibility

`talos.sv.source.conditional_expression` (::talos::ir::SVSourceConditionalExpressionOp)¶

Unbound conditional operation in an original default

Syntax:

operation ::= `talos.sv.source.conditional_expression` attr-dict-with-keyword $body

Owns the condition, true expression, and false expression in source order. None of the branches is selected or evaluated during source import.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.source.declared_type` (::talos::ir::SVSourceDeclaredTypeOp)¶

Exact parameter-independent source declared type

Syntax:

operation ::= `talos.sv.source.declared_type` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.source.declared_type_reference` (::talos::ir::SVSourceDeclaredTypeReferenceOp)¶

Source declared type naming an exact preceding lexical type

Syntax:

operation ::= `talos.sv.source.declared_type_reference` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: SymbolUserOpInterface

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`declaration`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

`talos.sv.source.parameter_actual` (::talos::ir::SVSourceParameterActualOp)¶

An exact explicit scalar-instance parameter connection

Syntax:

operation ::= `talos.sv.source.parameter_actual` attr-dict-with-keyword $body

The source node belongs to the instantiating instance body. Its parameter names an exact nonlocal declaration in a directly instantiated child body. A supported original value/type is its single child. Unsupported syntax and named empty connections are explicit, without substituting an effective parameter value/type. Ordinals distinguish source assignment occurrences.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: SymbolUserOpInterface

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`parameter`	::mlir::SymbolRefAttr	symbol reference attribute
`ordinal`	::mlir::IntegerAttr	64-bit signless integer attribute
`is_named`	::mlir::UnitAttr	unit attribute
`use_default`	::mlir::UnitAttr	unit attribute
`unavailable_rhs`	::mlir::StringAttr	string attribute

`talos.sv.source.parameter_reference` (::talos::ir::SVSourceParameterReferenceOp)¶

Exact preceding value parameter in an original default

Syntax:

operation ::= `talos.sv.source.parameter_reference` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: SymbolUserOpInterface

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`parameter`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

`talos.sv.source.type_default` (::talos::ir::SVSourceTypeDefaultOp)¶

Parameter-independent original type default

Syntax:

operation ::= `talos.sv.source.type_default` attr-dict-with-keyword $body

An exact concrete source type, without evaluating a class specialization. The existing vpi_typedef_layers metadata may retain alias spelling. This node has an empty body and is owned by a source type parameter.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.source.type_parameter` (::talos::ir::SVSourceTypeParameterSymbolOp)¶

Unresolved lexical type parameter of a generic class

Syntax:

operation ::= `talos.sv.source.type_parameter` $sym_name attr-dict-with-keyword $body

The direct parent is a lexical class definition. semantic_type is absent; the symbol itself is the unresolved typespec (IEEE 1800-2023 37.25 detail 11). Its body contains zero or one original type default. An empty body means there was no default, while an unsupported-default child preserves the distinct case where a source default has no structural import yet.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_local_param`	::mlir::UnitAttr	unit attribute

`talos.sv.source.type_reference_default` (::talos::ir::SVSourceTypeReferenceDefaultOp)¶

Original default naming a preceding lexical type parameter

Syntax:

operation ::= `talos.sv.source.type_reference_default` attr-dict-with-keyword $body

The symbol reference names the exact preceding source type parameter in the same generic class. This node does not bind or resolve that parameter. It has an empty body and is owned by another source type parameter.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: SymbolUserOpInterface

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`parameter`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

`talos.sv.source.unary_expression` (::talos::ir::SVSourceUnaryExpressionOp)¶

Unbound pure unary operation in an original default

Syntax:

operation ::= `talos.sv.source.unary_expression` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`operator_kind`	::talos::ir::SVUnaryOperatorAttr	complete source-level SystemVerilog unary operator

`talos.sv.source.unavailable_type` (::talos::ir::SVSourceUnavailableTypeOp)¶

Source declared type awaiting structural import

Syntax:

operation ::= `talos.sv.source.unavailable_type` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`syntax`	::mlir::StringAttr	string attribute

`talos.sv.source.unsupported_default` (::talos::ir::SVSourceUnsupportedDefaultOp)¶

Present original default awaiting structural import

Syntax:

operation ::= `talos.sv.source.unsupported_default` attr-dict-with-keyword $body

Preserves a present default separately from an absent default without fabricating its value or type. Only unsupported nodes retain source text; supported defaults use typed operations. The body is empty.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`syntax`	::mlir::StringAttr	string attribute
`reason`	::mlir::StringAttr	string attribute

`talos.sv.source.value_default` (::talos::ir::SVSourceValueDefaultOp)¶

Original value-parameter default expression

Syntax:

operation ::= `talos.sv.source.value_default` attr-dict-with-keyword $body

Owns exactly one typed source expression, independently of the effective parameter initializer and its overrides. Integer literal nodes retain their self-determined semantic types; references and operators remain unbound.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.source.value_parameter` (::talos::ir::SVSourceValueParameterSymbolOp)¶

Lexical value parameter without an effective specialization

Syntax:

operation ::= `talos.sv.source.value_parameter` $sym_name attr-dict-with-keyword $body

Directly owned by a generic class definition. Its body contains at most one original default node; no semantic_type or elaborated value is bound.

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_local_param`	::mlir::UnitAttr	unit attribute

`talos.sv.statement.block` (::talos::ir::SVBlockStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.block` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`block_kind`	::talos::ir::SVStatementBlockKindAttr	SystemVerilog sequential or parallel statement block kind
`block_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`block_path`	::mlir::StringAttr	string attribute
`is_implicit_loop_scope`	::mlir::UnitAttr	unit attribute

`talos.sv.statement.break` (::talos::ir::SVBreakStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.break` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.case` (::talos::ir::SVCaseStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.case` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`condition_kind`	::talos::ir::SVCaseConditionAttr	SystemVerilog case matching mode
`check_kind`	::talos::ir::SVUniquePriorityCheckAttr	unique or priority runtime check
`item_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`item_label_counts`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`has_default`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.concurrent_assertion` (::talos::ir::SVConcurrentAssertionStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.concurrent_assertion` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`assertion_kind`	::talos::ir::SVAssertionKindAttr	immediate or concurrent assertion directive kind
`has_pass_action`	::mlir::BoolAttr	bool attribute
`has_fail_action`	::mlir::BoolAttr	bool attribute
`is_procedural`	::mlir::BoolAttr	bool attribute
`has_contextual_clock`	::mlir::BoolAttr	bool attribute
`starts_on_current_clock`	::mlir::BoolAttr	bool attribute
`is_static_time_zero_equivalent`	::mlir::BoolAttr	bool attribute
`default_clocking_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`default_clocking_path`	::mlir::StringAttr	string attribute
`has_default_disable`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.conditional` (::talos::ir::SVConditionalStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.conditional` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`check_kind`	::talos::ir::SVUniquePriorityCheckAttr	unique or priority runtime check
`condition_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`condition_pattern_flags`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`has_else`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.continue` (::talos::ir::SVContinueStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.continue` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.disable` (::talos::ir::SVDisableStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.disable` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`target_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`target_path`	::mlir::StringAttr	string attribute
`is_hierarchical`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.disable_fork` (::talos::ir::SVDisableForkStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.disable_fork` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.do_while_loop` (::talos::ir::SVDoWhileLoopStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.do_while_loop` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.empty` (::talos::ir::SVEmptyStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.empty` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.event_trigger` (::talos::ir::SVEventTriggerStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.event_trigger` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`is_nonblocking`	::mlir::BoolAttr	bool attribute
`has_timing_control`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.expression_statement` (::talos::ir::SVExpressionStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.expression_statement` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.for_loop` (::talos::ir::SVForLoopStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.for_loop` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`initializer_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`has_condition`	::mlir::BoolAttr	bool attribute
`step_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`has_local_variables`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.foreach_loop` (::talos::ir::SVForeachLoopStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.foreach_loop` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`loop_dimensions`	::mlir::ArrayAttr	Array of dictionary attributes

`talos.sv.statement.forever_loop` (::talos::ir::SVForeverLoopStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.forever_loop` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.immediate_assertion` (::talos::ir::SVImmediateAssertionStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.immediate_assertion` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`assertion_kind`	::talos::ir::SVAssertionKindAttr	immediate or concurrent assertion directive kind
`is_deferred`	::mlir::BoolAttr	bool attribute
`is_final`	::mlir::BoolAttr	bool attribute
`has_pass_action`	::mlir::BoolAttr	bool attribute
`has_fail_action`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.list` (::talos::ir::SVStatementListOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.list` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.pattern_case` (::talos::ir::SVPatternCaseStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.pattern_case` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`condition_kind`	::talos::ir::SVCaseConditionAttr	SystemVerilog case matching mode
`check_kind`	::talos::ir::SVUniquePriorityCheckAttr	unique or priority runtime check
`item_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`item_filter_flags`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`has_default`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.procedural_assign` (::talos::ir::SVProceduralAssignStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.procedural_assign` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`is_force`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.procedural_checker` (::talos::ir::SVProceduralCheckerStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.procedural_checker` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyProceduralCheckerMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`instance_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`instance_symbols`	::mlir::ArrayAttr	symbol ref array attribute
`instance_paths`	::mlir::ArrayAttr	string array attribute

`talos.sv.statement.procedural_deassign` (::talos::ir::SVProceduralDeassignStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.procedural_deassign` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`is_release`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.rand_case` (::talos::ir::SVRandCaseStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.rand_case` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`item_count`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.statement.rand_sequence` (::talos::ir::SVRandSequenceStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.rand_sequence` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.repeat_loop` (::talos::ir::SVRepeatLoopStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.repeat_loop` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.return` (::talos::ir::SVReturnStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.return` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.timed` (::talos::ir::SVTimedStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.timed` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.variable_declaration` (::talos::ir::SVVariableDeclStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.variable_declaration` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute

`talos.sv.statement.wait` (::talos::ir::SVWaitStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.wait` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.wait_fork` (::talos::ir::SVWaitForkStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.wait_fork` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.statement.wait_order` (::talos::ir::SVWaitOrderStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.wait_order` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`event_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`has_success_action`	::mlir::BoolAttr	bool attribute
`has_failure_action`	::mlir::BoolAttr	bool attribute

`talos.sv.statement.while_loop` (::talos::ir::SVWhileLoopStatementOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.statement.while_loop` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.symbol.anonymous_program` (::talos::ir::SVAnonymousProgramSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.anonymous_program` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.assertion_port` (::talos::ir::SVAssertionPortSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.assertion_port` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`direction`	::talos::ir::SVArgumentDirectionAttr	SystemVerilog port or argument direction
`has_default_value`	::mlir::BoolAttr	bool attribute
`is_local_variable`	::mlir::BoolAttr	bool attribute

`talos.sv.symbol.attribute` (::talos::ir::SVAttributeSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.attribute` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.checker` (::talos::ir::SVCheckerSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.checker` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode, TalosVerifyAssertionDeclarationMetadata

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`port_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`port_symbols`	::mlir::ArrayAttr	symbol ref array attribute
`port_paths`	::mlir::ArrayAttr	string array attribute

`talos.sv.symbol.checker_instance` (::talos::ir::SVCheckerInstanceSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.checker_instance` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode, TalosVerifyCheckerInstanceMetadata

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`referenced_checker_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_checker_path`	::mlir::StringAttr	string attribute
`connection_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`connection_formal_symbols`	::mlir::ArrayAttr	symbol ref array attribute
`connection_formal_paths`	::mlir::ArrayAttr	string array attribute
`connection_actual_kinds`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`connection_has_actual`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`connection_has_output_initial`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`connection_attribute_counts`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`is_procedural`	::mlir::BoolAttr	bool attribute

`talos.sv.symbol.checker_instance_body` (::talos::ir::SVCheckerInstanceBodySymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.checker_instance_body` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`referenced_checker_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_checker_path`	::mlir::StringAttr	string attribute
`parent_instance_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`parent_instance_path`	::mlir::StringAttr	string attribute
`instance_depth`	::mlir::IntegerAttr	64-bit signless integer attribute
`instance_flags`	::mlir::IntegerAttr	64-bit signless integer attribute
`is_procedural`	::mlir::BoolAttr	bool attribute

`talos.sv.symbol.class_property` (::talos::ir::SVClassPropertySymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.class_property` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`rand_mode`	::talos::ir::SVRandModeAttr	SystemVerilog randomization mode
`is_const`	::mlir::UnitAttr	unit attribute
`is_compiler_generated`	::mlir::UnitAttr	unit attribute
`is_immutable_coverage_option`	::mlir::UnitAttr	unit attribute
`is_coverage_sample_formal`	::mlir::UnitAttr	unit attribute
`is_checker_free_variable`	::mlir::UnitAttr	unit attribute
`is_ref_static`	::mlir::UnitAttr	unit attribute
`member_visibility`	::talos::ir::SVVisibilityAttr	SystemVerilog class member visibility

`talos.sv.symbol.clock_var` (::talos::ir::SVClockVarSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.clock_var` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`rand_mode`	::talos::ir::SVRandModeAttr	SystemVerilog randomization mode
`is_const`	::mlir::UnitAttr	unit attribute
`is_compiler_generated`	::mlir::UnitAttr	unit attribute
`is_immutable_coverage_option`	::mlir::UnitAttr	unit attribute
`is_coverage_sample_formal`	::mlir::UnitAttr	unit attribute
`is_checker_free_variable`	::mlir::UnitAttr	unit attribute
`is_ref_static`	::mlir::UnitAttr	unit attribute
`direction`	::talos::ir::SVArgumentDirectionAttr	SystemVerilog port or argument direction
`input_edge`	::talos::ir::EdgeKindAttr	SystemVerilog event edge
`output_edge`	::talos::ir::EdgeKindAttr	SystemVerilog event edge
`has_input_delay`	::mlir::BoolAttr	bool attribute
`has_output_delay`	::mlir::BoolAttr	bool attribute

`talos.sv.symbol.clocking_block` (::talos::ir::SVClockingBlockSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.clocking_block` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_default`	::mlir::BoolAttr	bool attribute
`is_global`	::mlir::BoolAttr	bool attribute

`talos.sv.symbol.compilation_unit` (::talos::ir::SVCompilationUnitSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.compilation_unit` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.config_block` (::talos::ir::SVConfigBlockSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.config_block` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.constraint_block` (::talos::ir::SVConstraintBlockSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.constraint_block` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_pure`	::mlir::UnitAttr	unit attribute
`is_static`	::mlir::UnitAttr	unit attribute
`is_extern`	::mlir::UnitAttr	unit attribute
`is_explicit_extern`	::mlir::UnitAttr	unit attribute
`is_initial`	::mlir::UnitAttr	unit attribute
`is_extends`	::mlir::UnitAttr	unit attribute
`is_final`	::mlir::UnitAttr	unit attribute
`out_of_block_index`	::mlir::IntegerAttr	64-bit signless integer attribute
`this_variable_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`this_variable_path`	::mlir::StringAttr	string attribute

`talos.sv.symbol.continuous_assign` (::talos::ir::SVContinuousAssignSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.continuous_assign` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`drive_strength0`	::talos::ir::SVDriveStrengthAttr	SystemVerilog drive strength for one logic polarity
`drive_strength1`	::talos::ir::SVDriveStrengthAttr	SystemVerilog drive strength for one logic polarity
`delay_fs`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`unsupported_delay`	::mlir::StringAttr	string attribute

`talos.sv.symbol.cover_cross` (::talos::ir::SVCoverCrossSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.cover_cross` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosCoverageCrossNode, TalosSemanticASTNode, TalosVerifyCoverCrossMetadata

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`target_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`target_symbols`	::mlir::ArrayAttr	symbol ref array attribute
`has_iff`	::mlir::BoolAttr	bool attribute
`option_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`expression_roles`	::mlir::ArrayAttr	coverage expression role array

`talos.sv.symbol.cover_cross_body` (::talos::ir::SVCoverCrossBodySymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.cover_cross_body` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.coverage_bin` (::talos::ir::SVCoverageBinSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.coverage_bin` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageBinNode, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyCoverageBinMetadata

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`bins_kind`	::talos::ir::SVCoverageBinKindAttr	coverage bin classification
`is_array`	::mlir::BoolAttr	bool attribute
`is_wildcard`	::mlir::BoolAttr	bool attribute
`is_default`	::mlir::BoolAttr	bool attribute
`is_default_sequence`	::mlir::BoolAttr	bool attribute
`has_iff`	::mlir::BoolAttr	bool attribute
`has_number_of_bins`	::mlir::BoolAttr	bool attribute
`has_set_coverage`	::mlir::BoolAttr	bool attribute
`has_with`	::mlir::BoolAttr	bool attribute
`value_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`transition_set_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`child_roles`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`transition_set_range_counts`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`transition_range_item_counts`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`transition_range_repeat_kinds`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`transition_range_has_repeat_from`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`transition_range_has_repeat_to`	::mlir::DenseI64ArrayAttr	i64 dense array attribute

`talos.sv.symbol.covergroup_body` (::talos::ir::SVCovergroupBodySymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.covergroup_body` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode, TalosVerifyCoverageOptionContainerMetadata

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`option_count`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.symbol.coverpoint` (::talos::ir::SVCoverpointSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.coverpoint` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosCoveragePointNode, TalosSemanticASTNode, TalosVerifyCoverpointMetadata

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`has_iff`	::mlir::BoolAttr	bool attribute
`has_explicit_type`	::mlir::BoolAttr	bool attribute
`option_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`expression_roles`	::mlir::ArrayAttr	coverage expression role array

`talos.sv.symbol.def_param` (::talos::ir::SVDefParamSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.def_param` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.definition` (::talos::ir::SVDefinitionSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.definition` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`definition_kind`	::talos::ir::SVDefinitionKindAttr	SystemVerilog design-unit definition kind

`talos.sv.symbol.elab_system_task` (::talos::ir::SVElabSystemTaskSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.elab_system_task` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.empty_member` (::talos::ir::SVEmptyMemberSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.empty_member` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.enum_value` (::talos::ir::SVEnumValueSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.enum_value` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`constant_value`	::mlir::StringAttr	string attribute

`talos.sv.symbol.explicit_import` (::talos::ir::SVExplicitImportSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.explicit_import` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.field` (::talos::ir::SVFieldSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.field` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosAggregateFieldNode, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`rand_mode`	::talos::ir::SVRandModeAttr	SystemVerilog randomization mode
`is_const`	::mlir::UnitAttr	unit attribute
`is_compiler_generated`	::mlir::UnitAttr	unit attribute
`is_immutable_coverage_option`	::mlir::UnitAttr	unit attribute
`is_coverage_sample_formal`	::mlir::UnitAttr	unit attribute
`is_checker_free_variable`	::mlir::UnitAttr	unit attribute
`is_ref_static`	::mlir::UnitAttr	unit attribute
`bit_offset`	::mlir::IntegerAttr	64-bit signless integer attribute
`field_index`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.symbol.formal_argument` (::talos::ir::SVFormalArgumentSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.formal_argument` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosFormalArgumentNode, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`rand_mode`	::talos::ir::SVRandModeAttr	SystemVerilog randomization mode
`is_const`	::mlir::UnitAttr	unit attribute
`is_compiler_generated`	::mlir::UnitAttr	unit attribute
`is_immutable_coverage_option`	::mlir::UnitAttr	unit attribute
`is_coverage_sample_formal`	::mlir::UnitAttr	unit attribute
`is_checker_free_variable`	::mlir::UnitAttr	unit attribute
`is_ref_static`	::mlir::UnitAttr	unit attribute
`direction`	::talos::ir::SVArgumentDirectionAttr	SystemVerilog port or argument direction
`merged_variable_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`merged_variable_path`	::mlir::StringAttr	string attribute

`talos.sv.symbol.forwarding_typedef` (::talos::ir::SVForwardingTypedefSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.forwarding_typedef` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.generate_block` (::talos::ir::SVGenerateBlockSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.generate_block` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.generate_block_array` (::talos::ir::SVGenerateBlockArraySymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.generate_block_array` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`array_indices`	::mlir::DenseI64ArrayAttr	i64 dense array attribute

`talos.sv.symbol.generic_class_def` (::talos::ir::SVGenericClassDefSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.generic_class_def` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Interfaces: SymbolUserOpInterface, Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_interface`	::mlir::BoolAttr	bool attribute
`lexical_definition`	::mlir::SymbolRefAttr	symbol reference attribute
`specialization_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`first_forward_declaration_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`first_forward_declaration_path`	::mlir::StringAttr	string attribute

`talos.sv.symbol.genvar` (::talos::ir::SVGenvarSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.genvar` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.instance` (::talos::ir::SVInstanceSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.instance` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`referenced_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`referenced_path`	::mlir::StringAttr	string attribute
`is_uninstantiated`	::mlir::BoolAttr	bool attribute
`is_virtual_interface_type_instance`	::mlir::BoolAttr	bool attribute

`talos.sv.symbol.instance_array` (::talos::ir::SVInstanceArraySymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.instance_array` $sym_name attr-dict-with-keyword $body

The body contains one element per source index in ascending numeric index order, independent of the declared direction in array_range. Nested instance-array nodes repeat this contract for the next dimension.

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`array_range`	::mlir::DenseI64ArrayAttr	i64 dense array attribute

`talos.sv.symbol.instance_body` (::talos::ir::SVInstanceBodySymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.instance_body` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.interface_port` (::talos::ir::SVInterfacePortSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.interface_port` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.iterator` (::talos::ir::SVIteratorSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.iterator` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`rand_mode`	::talos::ir::SVRandModeAttr	SystemVerilog randomization mode
`is_const`	::mlir::UnitAttr	unit attribute
`is_compiler_generated`	::mlir::UnitAttr	unit attribute
`is_immutable_coverage_option`	::mlir::UnitAttr	unit attribute
`is_coverage_sample_formal`	::mlir::UnitAttr	unit attribute
`is_checker_free_variable`	::mlir::UnitAttr	unit attribute
`is_ref_static`	::mlir::UnitAttr	unit attribute
`array_type`	::mlir::TypeAttr	any type attribute
`index_method_name`	::mlir::StringAttr	string attribute

`talos.sv.symbol.let_decl` (::talos::ir::SVLetDeclSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.let_decl` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.local_assertion_var` (::talos::ir::SVLocalAssertionVarSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.local_assertion_var` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`rand_mode`	::talos::ir::SVRandModeAttr	SystemVerilog randomization mode
`is_const`	::mlir::UnitAttr	unit attribute
`is_compiler_generated`	::mlir::UnitAttr	unit attribute
`is_immutable_coverage_option`	::mlir::UnitAttr	unit attribute
`is_coverage_sample_formal`	::mlir::UnitAttr	unit attribute
`is_checker_free_variable`	::mlir::UnitAttr	unit attribute
`is_ref_static`	::mlir::UnitAttr	unit attribute
`formal_port_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`formal_port_path`	::mlir::StringAttr	string attribute

`talos.sv.symbol.method_prototype` (::talos::ir::SVMethodPrototypeSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.method_prototype` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`subroutine_kind`	::talos::ir::SVSubroutineKindAttr	SystemVerilog function or task kind
`member_visibility`	::talos::ir::SVVisibilityAttr	SystemVerilog class member visibility
`is_virtual`	::mlir::UnitAttr	unit attribute
`is_declared_virtual`	::mlir::UnitAttr	unit attribute
`is_pure`	::mlir::UnitAttr	unit attribute
`is_static`	::mlir::UnitAttr	unit attribute
`is_constructor`	::mlir::UnitAttr	unit attribute
`is_interface_extern`	::mlir::UnitAttr	unit attribute
`is_modport_import`	::mlir::UnitAttr	unit attribute
`is_modport_export`	::mlir::UnitAttr	unit attribute
`is_dpi_import`	::mlir::UnitAttr	unit attribute
`is_dpi_context`	::mlir::UnitAttr	unit attribute
`dpi_c_identifier`	::mlir::StringAttr	string attribute
`dpi_export_c_identifier`	::mlir::StringAttr	string attribute
`is_builtin`	::mlir::UnitAttr	unit attribute
`is_fork_join`	::mlir::UnitAttr	unit attribute
`has_defaulted_super_arg`	::mlir::UnitAttr	unit attribute
`is_initial`	::mlir::UnitAttr	unit attribute
`is_extends`	::mlir::UnitAttr	unit attribute
`is_final`	::mlir::UnitAttr	unit attribute
`subroutine_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`subroutine_path`	::mlir::StringAttr	string attribute
`override_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`override_path`	::mlir::StringAttr	string attribute
`extern_implementation_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`extern_implementation_symbols`	::mlir::ArrayAttr	symbol ref array attribute
`extern_implementation_paths`	::mlir::ArrayAttr	string array attribute

`talos.sv.symbol.modport` (::talos::ir::SVModportSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.modport` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.modport_clocking` (::talos::ir::SVModportClockingSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.modport_clocking` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.modport_port` (::talos::ir::SVModportPortSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.modport_port` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.multi_port` (::talos::ir::SVMultiPortSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.multi_port` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`direction`	::talos::ir::SVArgumentDirectionAttr	SystemVerilog port or argument direction

`talos.sv.symbol.net` (::talos::ir::SVNetSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.net` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`net_kind`	::talos::ir::SVNetKindAttr	SystemVerilog net resolution kind
`is_implicit`	::mlir::BoolAttr	bool attribute
`expansion_hint`	::talos::ir::SVNetExpansionHintAttr	explicit SystemVerilog net vector expansion request
`nettype_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`nettype_path`	::mlir::StringAttr	string attribute
`resolution_function_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`resolution_function_path`	::mlir::StringAttr	string attribute
`drive_strength0`	::talos::ir::SVDriveStrengthAttr	SystemVerilog drive strength for one logic polarity
`drive_strength1`	::talos::ir::SVDriveStrengthAttr	SystemVerilog drive strength for one logic polarity
`charge_strength`	::talos::ir::SVChargeStrengthAttr	SystemVerilog trireg charge strength
`delay_fs`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`unsupported_delay`	::mlir::StringAttr	string attribute

`talos.sv.symbol.net_alias` (::talos::ir::SVNetAliasSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.net_alias` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.package` (::talos::ir::SVPackageSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.package` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.parameter` (::talos::ir::SVParameterSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.parameter` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`constant_value`	::mlir::StringAttr	string attribute
`is_local_param`	::mlir::UnitAttr	unit attribute
`has_explicit_range`	::mlir::UnitAttr	unit attribute

`talos.sv.symbol.pattern_var` (::talos::ir::SVPatternVarSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.pattern_var` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosPatternBindingNode, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`rand_mode`	::talos::ir::SVRandModeAttr	SystemVerilog randomization mode
`is_const`	::mlir::UnitAttr	unit attribute
`is_compiler_generated`	::mlir::UnitAttr	unit attribute
`is_immutable_coverage_option`	::mlir::UnitAttr	unit attribute
`is_coverage_sample_formal`	::mlir::UnitAttr	unit attribute
`is_checker_free_variable`	::mlir::UnitAttr	unit attribute
`is_ref_static`	::mlir::UnitAttr	unit attribute

`talos.sv.symbol.port` (::talos::ir::SVPortSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.port` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`direction`	::talos::ir::SVArgumentDirectionAttr	SystemVerilog port or argument direction

`talos.sv.symbol.primitive` (::talos::ir::SVPrimitiveSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.primitive` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.primitive_instance` (::talos::ir::SVPrimitiveInstanceSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.primitive_instance` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`drive_strength0`	::talos::ir::SVDriveStrengthAttr	SystemVerilog drive strength for one logic polarity
`drive_strength1`	::talos::ir::SVDriveStrengthAttr	SystemVerilog drive strength for one logic polarity
`delay_fs`	::mlir::DenseI64ArrayAttr	i64 dense array attribute
`unsupported_delay`	::mlir::StringAttr	string attribute

`talos.sv.symbol.primitive_port` (::talos::ir::SVPrimitivePortSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.primitive_port` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.procedural_block` (::talos::ir::SVProceduralBlockSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.procedural_block` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`procedure_kind`	::talos::ir::SVProceduralBlockKindAttr	SystemVerilog procedural block kind

`talos.sv.symbol.property` (::talos::ir::SVPropertySymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.property` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode, TalosVerifyAssertionDeclarationMetadata

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`port_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`port_symbols`	::mlir::ArrayAttr	symbol ref array attribute
`port_paths`	::mlir::ArrayAttr	string array attribute
`has_default_instance`	::mlir::BoolAttr	bool attribute
`default_clocking_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`default_clocking_path`	::mlir::StringAttr	string attribute

`talos.sv.symbol.pulse_style` (::talos::ir::SVPulseStyleSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.pulse_style` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.rand_seq_production` (::talos::ir::SVRandSeqProductionSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.rand_seq_production` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.root` (::talos::ir::SVRootSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.root` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode, TalosSemanticReferenceRootNode, TalosVerifySemanticReferenceGraph

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.sequence` (::talos::ir::SVSequenceSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.sequence` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode, TalosVerifyAssertionDeclarationMetadata

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`port_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`port_symbols`	::mlir::ArrayAttr	symbol ref array attribute
`port_paths`	::mlir::ArrayAttr	string array attribute
`has_default_instance`	::mlir::BoolAttr	bool attribute
`default_clocking_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`default_clocking_path`	::mlir::StringAttr	string attribute

`talos.sv.symbol.specify_block` (::talos::ir::SVSpecifyBlockSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.specify_block` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.specparam` (::talos::ir::SVSpecparamSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.specparam` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`constant_value`	::mlir::StringAttr	string attribute

`talos.sv.symbol.statement_block` (::talos::ir::SVStatementBlockSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.statement_block` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`block_kind`	::talos::ir::SVStatementBlockKindAttr	SystemVerilog sequential or parallel statement block kind

`talos.sv.symbol.subroutine` (::talos::ir::SVSubroutineSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.subroutine` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`subroutine_kind`	::talos::ir::SVSubroutineKindAttr	SystemVerilog function or task kind
`default_lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`member_visibility`	::talos::ir::SVVisibilityAttr	SystemVerilog class member visibility
`is_virtual`	::mlir::UnitAttr	unit attribute
`is_declared_virtual`	::mlir::UnitAttr	unit attribute
`is_pure`	::mlir::UnitAttr	unit attribute
`is_static`	::mlir::UnitAttr	unit attribute
`is_constructor`	::mlir::UnitAttr	unit attribute
`is_interface_extern`	::mlir::UnitAttr	unit attribute
`is_modport_import`	::mlir::UnitAttr	unit attribute
`is_modport_export`	::mlir::UnitAttr	unit attribute
`is_dpi_import`	::mlir::UnitAttr	unit attribute
`is_dpi_context`	::mlir::UnitAttr	unit attribute
`dpi_c_identifier`	::mlir::StringAttr	string attribute
`dpi_export_c_identifier`	::mlir::StringAttr	string attribute
`is_builtin`	::mlir::UnitAttr	unit attribute
`is_randomize`	::mlir::UnitAttr	unit attribute
`is_fork_join`	::mlir::UnitAttr	unit attribute
`has_defaulted_super_arg`	::mlir::UnitAttr	unit attribute
`is_initial`	::mlir::UnitAttr	unit attribute
`is_extends`	::mlir::UnitAttr	unit attribute
`is_final`	::mlir::UnitAttr	unit attribute
`is_pre_post_randomize`	::mlir::UnitAttr	unit attribute
`out_of_block_index`	::mlir::IntegerAttr	64-bit signless integer attribute
`override_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`override_path`	::mlir::StringAttr	string attribute
`prototype_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`prototype_path`	::mlir::StringAttr	string attribute
`return_variable_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`return_variable_path`	::mlir::StringAttr	string attribute
`this_variable_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`this_variable_path`	::mlir::StringAttr	string attribute

`talos.sv.symbol.system_timing_check` (::talos::ir::SVSystemTimingCheckSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.system_timing_check` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.timing_path` (::talos::ir::SVTimingPathSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.timing_path` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.transparent_member` (::talos::ir::SVTransparentMemberSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.transparent_member` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.type_parameter` (::talos::ir::SVTypeParameterSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.type_parameter` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_local_param`	::mlir::UnitAttr	unit attribute

`talos.sv.symbol.uninstantiated_def` (::talos::ir::SVUninstantiatedDefSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.uninstantiated_def` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.symbol.variable` (::talos::ir::SVVariableSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.variable` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`lifetime`	::talos::ir::SVVariableLifetimeAttr	SystemVerilog variable storage lifetime
`rand_mode`	::talos::ir::SVRandModeAttr	SystemVerilog randomization mode
`is_const`	::mlir::UnitAttr	unit attribute
`is_compiler_generated`	::mlir::UnitAttr	unit attribute
`is_immutable_coverage_option`	::mlir::UnitAttr	unit attribute
`is_coverage_sample_formal`	::mlir::UnitAttr	unit attribute
`is_checker_free_variable`	::mlir::UnitAttr	unit attribute
`is_ref_static`	::mlir::UnitAttr	unit attribute

`talos.sv.symbol.wildcard_import` (::talos::ir::SVWildcardImportSymbolOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.symbol.wildcard_import` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.timing.block_event_list` (::talos::ir::SVBlockEventListControlOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.timing.block_event_list` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageBlockEventNode, TalosSemanticASTNode, TalosSemanticTimingNode, TalosVerifyCoverageBlockEventMetadata

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`event_kinds`	::mlir::ArrayAttr	coverage block-event kind array

`talos.sv.timing.cycle_delay` (::talos::ir::SVCycleDelayControlOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.timing.cycle_delay` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticTimingNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.timing.delay` (::talos::ir::SVDelayControlOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.timing.delay` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticTimingNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.timing.delay3` (::talos::ir::SVDelay3ControlOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.timing.delay3` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticTimingNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`delay_count`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.timing.event_list` (::talos::ir::SVEventListControlOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.timing.event_list` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageClockingEventNode, TalosSemanticASTNode, TalosSemanticTimingNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`event_count`	::mlir::IntegerAttr	64-bit signless integer attribute

`talos.sv.timing.implicit_event` (::talos::ir::SVImplicitEventControlOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.timing.implicit_event` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticTimingNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.timing.invalid` (::talos::ir::SVInvalidTimingControlOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.timing.invalid` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosRejectInvalidSemanticNode, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.timing.one_step_delay` (::talos::ir::SVOneStepDelayControlOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.timing.one_step_delay` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticTimingNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.timing.repeated_event` (::talos::ir::SVRepeatedEventControlOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.timing.repeated_event` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode, TalosSemanticTimingNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.timing.signal_event` (::talos::ir::SVSignalEventControlOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.timing.signal_event` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosCoverageClockingEventNode, TalosSemanticASTNode, TalosSemanticTimingNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`edge_kind`	::talos::ir::EdgeKindAttr	SystemVerilog event edge
`has_iff`	::mlir::BoolAttr	bool attribute

`talos.sv.type.associative_array_type` (::talos::ir::SVAssociativeArrayTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.associative_array_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.c_handle_type` (::talos::ir::SVCHandleTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.c_handle_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.class_type` (::talos::ir::SVClassTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.class_type` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode, TalosSemanticDeclarativeNode

Interfaces: SymbolUserOpInterface, Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`is_abstract`	::mlir::BoolAttr	bool attribute
`lexical_definition`	::mlir::SymbolRefAttr	symbol reference attribute
`is_interface`	::mlir::BoolAttr	bool attribute
`is_final`	::mlir::BoolAttr	bool attribute
`is_uninstantiated`	::mlir::BoolAttr	bool attribute
`base_class`	::mlir::TypeAttr	any type attribute
`implemented_interfaces`	::mlir::ArrayAttr	type array attribute
`declared_interfaces`	::mlir::ArrayAttr	type array attribute
`generic_class_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`generic_class_path`	::mlir::StringAttr	string attribute
`generic_parameter_symbols`	::mlir::ArrayAttr	symbol ref array attribute
`generic_parameter_paths`	::mlir::ArrayAttr	string array attribute
`this_variable_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`this_variable_path`	::mlir::StringAttr	string attribute
`constructor_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`constructor_path`	::mlir::StringAttr	string attribute
`has_base_constructor_call`	::mlir::BoolAttr	bool attribute
`bitstream_width`	::mlir::IntegerAttr	64-bit signless integer attribute
`has_cycles`	::mlir::BoolAttr	bool attribute

`talos.sv.type.covergroup_type` (::talos::ir::SVCovergroupTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.covergroup_type` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosCoverageGroupNode, TalosSemanticASTNode, TalosSemanticDeclarativeNode, TalosVerifyCovergroupTypeMetadata

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`base_group`	::mlir::TypeAttr	any type attribute
`constructor_argument_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`constructor_formals`	::mlir::ArrayAttr	symbol ref array attribute
`sample_formal_count`	::mlir::IntegerAttr	64-bit signless integer attribute
`sample_formals`	::mlir::ArrayAttr	symbol ref array attribute
`coverage_event_kind`	::talos::ir::SVCoverageEventKindAttr	declared covergroup sampling form
`has_coverage_event`	::mlir::BoolAttr	bool attribute

`talos.sv.type.dpi_open_array_type` (::talos::ir::SVDPIOpenArrayTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.dpi_open_array_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.dynamic_array_type` (::talos::ir::SVDynamicArrayTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.dynamic_array_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.enum_type` (::talos::ir::SVEnumTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.enum_type` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.error_type` (::talos::ir::SVErrorTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.error_type` attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosRejectInvalidSemanticNode, TalosSemanticASTNode

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute

`talos.sv.type.event_type` (::talos::ir::SVEventTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.event_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.fixed_size_unpacked_array_type` (::talos::ir::SVFixedSizeUnpackedArrayTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.fixed_size_unpacked_array_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.floating_type` (::talos::ir::SVFloatingTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.floating_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.net_type` (::talos::ir::SVNetTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.net_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute
`net_kind`	::talos::ir::SVNetKindAttr	SystemVerilog net resolution kind
`data_type`	::mlir::TypeAttr	any type attribute
`is_builtin`	::mlir::BoolAttr	bool attribute
`aliased_nettype_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`aliased_nettype_path`	::mlir::StringAttr	string attribute
`resolution_function_symbol`	::mlir::SymbolRefAttr	symbol reference attribute
`resolution_function_path`	::mlir::StringAttr	string attribute

`talos.sv.type.null_type` (::talos::ir::SVNullTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.null_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.packed_array_type` (::talos::ir::SVPackedArrayTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.packed_array_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.packed_struct_type` (::talos::ir::SVPackedStructTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.packed_struct_type` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.packed_union_type` (::talos::ir::SVPackedUnionTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.packed_union_type` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.predefined_integer_type` (::talos::ir::SVPredefinedIntegerTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.predefined_integer_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.property_type` (::talos::ir::SVPropertyTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.property_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.queue_type` (::talos::ir::SVQueueTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.queue_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.scalar_type` (::talos::ir::SVScalarTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.scalar_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.sequence_type` (::talos::ir::SVSequenceTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.sequence_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.string_type` (::talos::ir::SVStringTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.string_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.type_alias` (::talos::ir::SVTypeAliasTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.type_alias` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.type_ref_type` (::talos::ir::SVTypeRefTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.type_ref_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.unbounded_type` (::talos::ir::SVUnboundedTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.unbounded_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.unpacked_struct_type` (::talos::ir::SVUnpackedStructTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.unpacked_struct_type` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.unpacked_union_type` (::talos::ir::SVUnpackedUnionTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.unpacked_union_type` $sym_name attr-dict-with-keyword $body

Traits: IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.untyped_type` (::talos::ir::SVUntypedTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.untyped_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.virtual_interface_type` (::talos::ir::SVVirtualInterfaceTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.virtual_interface_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.sv.type.void_type` (::talos::ir::SVVoidTypeOp)¶

Concrete high-level elaborated SystemVerilog operation

Syntax:

operation ::= `talos.sv.type.void_type` $sym_name attr-dict-with-keyword $body

Traits: NoTerminator, SingleBlock, TalosSemanticASTNode

Interfaces: Symbol

Attributes:¶

Attribute	MLIR Type	Description
`node_id`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_range`	::mlir::TypeAttr	any type attribute
`original_source_range`	::mlir::TypeAttr	any type attribute
`macro_expansion_stack`	::mlir::ArrayAttr	Array of dictionary attributes
`source_file`	::mlir::StringAttr	string attribute
`source_end_line`	::mlir::IntegerAttr	64-bit signless integer attribute
`source_end_column`	::mlir::IntegerAttr	64-bit signless integer attribute
`macro_name`	::mlir::StringAttr	string attribute
`sym_name`	::mlir::StringAttr	string attribute
`name`	::mlir::StringAttr	string attribute
`hierarchical_name`	::mlir::StringAttr	string attribute
`semantic_type`	::mlir::TypeAttr	any type attribute

`talos.system.call` (::talos::ir::SystemCallOp)¶

Effectful built-in or PLI system task/function

Syntax:

operation ::= `talos.system.call` $name `(` $arguments `)` attr-dict `:`
              functional-type($arguments, $results)

Attributes:¶

Attribute	MLIR Type	Description
`name`	::mlir::StringAttr	string attribute

Operands:¶

Operand	Description
`arguments`	variadic of any type

Results:¶

Result	Description
`results`	variadic of any type

`talos.time.add` (::talos::ir::TimeAddOp)¶

Add scaled simulation times with defined overflow handling

Syntax:

operation ::= `talos.time.add` $lhs `,` $rhs attr-dict

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`lhs`	scaled simulation time
`rhs`	scaled simulation time

Results:¶

Result	Description
`result`	scaled simulation time

`talos.time.constant` (::talos::ir::TimeConstantOp)¶

Simulation time constant in design precision units

Syntax:

operation ::= `talos.time.constant` $value attr-dict

Traits: AlwaysSpeculatableImplTrait, ConstantLike

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:¶

Attribute	MLIR Type	Description
`value`	::mlir::IntegerAttr	arbitrary integer attribute

Results:¶

Result	Description
`result`	scaled simulation time

`talos.trace` (::talos::ir::TraceOp)¶

Emit a timestamped trace value

Syntax:

operation ::= `talos.trace` $hierarchicalName `=` $value `at` $time attr-dict `:` type($value)

Attributes:¶

Attribute	MLIR Type	Description
`hierarchicalName`	::mlir::StringAttr	string attribute

Operands:¶

Operand	Description
`value`	any type
`time`	scaled simulation time

`talos.unbox` (::talos::ir::UnboxOp)¶

Checked extraction from a boxed runtime value

Syntax:

operation ::= `talos.unbox` $input attr-dict `:` qualified(type($input)) `->` type($result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:¶

Operand	Description
`input`	boxed runtime value for untyped containers and reflection

Results:¶

Result	Description
`result`	any type

`talos.var.alloc` (::talos::ir::VarAllocOp)¶

Allocate process, automatic, or scope storage

Syntax:

operation ::= `talos.var.alloc` (`=` $initialValue^ `:` type($initialValue))? attr-dict `:`
              qualified(type($result))

Operands:¶

Operand	Description
`initialValue`	any type

Results:¶

Result	Description
`result`	mutable variable or object-field reference

`talos.vpi.callback` (::talos::ir::VPICallbackOp)¶

Register a callback at an explicit scheduler observation point

Syntax:

operation ::= `talos.vpi.callback` $callback `for` $reason `on` $handle `in` $region attr-dict

Attributes:¶

Attribute	MLIR Type	Description
`reason`	::mlir::IntegerAttr	32-bit signless integer attribute
`region`	::talos::ir::EventRegionAttr	IEEE 1800 event region
`callback`	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Operands:¶

Operand	Description
`handle`	opaque VPI object handle

`talos.vpi.get` (::talos::ir::VPIGetOp)¶

Read a reflected VPI property or value

Syntax:

operation ::= `talos.vpi.get` $property `from` $handle attr-dict

Attributes:¶

Attribute	MLIR Type	Description
`property`	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:¶

Operand	Description
`handle`	opaque VPI object handle

Results:¶

Result	Description
`result`	boxed runtime value for untyped containers and reflection

`talos.vpi.put` (::talos::ir::VPIPutOp)¶

Write, force, release, or deposit through VPI

Syntax:

operation ::= `talos.vpi.put` $property `of` $handle `=` $value (`after` $delay^)? attr-dict

Attributes:¶

Attribute	MLIR Type	Description
`property`	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:¶

Operand	Description
`handle`	opaque VPI object handle
`value`	boxed runtime value for untyped containers and reflection
`delay`	scaled simulation time

Types¶

AssocArrayType¶

Associative array with reference semantics

Syntax:

!talos.assoc<
  ::mlir::Type,   # keyType
  ::mlir::Type,   # elementType
  bool   # wildcardIndex
>

Parameters:¶

Parameter	C++ type	Description
keyType	`::mlir::Type`
elementType	`::mlir::Type`
wildcardIndex	`bool`

BoxType¶

Boxed runtime value for untyped containers and reflection

Syntax: !talos.any

ChandleType¶

Opaque DPI C pointer

Syntax: !talos.chandle

ClassHandleType¶

Nullable statically typed SystemVerilog class handle

Syntax:

!talos.class_handle<
  ::mlir::SymbolRefAttr   # className
>

Parameters:¶

Parameter	C++ type	Description
className	`::mlir::SymbolRefAttr`

ConstraintSetType¶

Compiled random constraint graph handle

Syntax: !talos.constraint_set

CovergroupHandleType¶

Syntax:

!talos.covergroup_handle<
  ::mlir::SymbolRefAttr   # covergroupName
>

Parameters:¶

Parameter	C++ type	Description
covergroupName	`::mlir::SymbolRefAttr`

DynArrayType¶

Dynamic array with reference semantics

Syntax:

!talos.dynarray<
  ::mlir::Type   # elementType
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`

EnumType¶

Syntax:

!talos.enum<
  ::mlir::StringAttr,   # name
  ::mlir::Type   # baseType
>

Parameters:¶

Parameter	C++ type	Description
name	`::mlir::StringAttr`
baseType	`::mlir::Type`

ErrorType¶

Syntax:

!talos.error<
  bool   # invalid
>

Parameters:¶

Parameter	C++ type	Description
invalid	`bool`

EventType¶

Named event handle

Syntax: !talos.event

IntegralType¶

Range-preserving elaborated integral type

Syntax:

!talos.integral<
  unsigned,   # width
  bool,   # isSigned
  bool,   # isFourState
  int64_t,   # left
  int64_t,   # right
  ::talos::ir::SVIntegralFlavor   # flavor
>

Parameters:¶

Parameter	C++ type	Description
width	`unsigned`
isSigned	`bool`
isFourState	`bool`
left	`int64_t`
right	`int64_t`
flavor	`::talos::ir::SVIntegralFlavor`	an enum of type SVIntegralFlavor

LogicType¶

Fixed-width exact four-state packed value

Syntax:

!talos.logic<
  unsigned   # width
>

Parameters:¶

Parameter	C++ type	Description
width	`unsigned`

MailboxType¶

Typed or boxed blocking mailbox

Syntax:

!talos.mailbox<
  ::mlir::Type   # elementType
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`

NetType¶

Resolved SystemVerilog net handle

Syntax:

!talos.net<
  ::mlir::Type   # elementType
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`

NullType¶

Polymorphic SystemVerilog null handle literal

Syntax: !talos.null

ObjectType¶

Nullable dynamically-dispatched class object handle

Syntax: !talos.object

OpenArrayType¶

Borrowed packed or unpacked open-array view

Syntax:

!talos.open_array<
  ::mlir::Type,   # elementType
  bool   # isPacked
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`
isPacked	`bool`

PackedArrayType¶

Fixed-size packed SystemVerilog array

Syntax:

!talos.packed_array<
  ::mlir::Type,   # elementType
  unsigned   # size
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`
size	`unsigned`

PackedStructType¶

Packed SystemVerilog struct

Syntax:

!talos.packed_struct<
  ::mlir::DictionaryAttr   # fields
>

Parameters:¶

Parameter	C++ type	Description
fields	`::mlir::DictionaryAttr`

PackedUnionType¶

Packed SystemVerilog union

Syntax:

!talos.packed_union<
  ::mlir::DictionaryAttr   # fields
>

Parameters:¶

Parameter	C++ type	Description
fields	`::mlir::DictionaryAttr`

ProcessType¶

Scheduler-owned process handle

Syntax: !talos.process

PropertyType¶

Syntax: !talos.property

QueueType¶

Syntax:

!talos.queue<
  ::mlir::Type,   # elementType
  uint32_t   # bound
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`
bound	`uint32_t`

RandCStateType¶

State for a random-cyclic variable

Syntax:

!talos.randc_state<
  ::mlir::Type   # elementType
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`

RandomStateType¶

Saved random stream state

Syntax: !talos.random_state

RandomStreamType¶

Deterministic hierarchical pseudorandom stream

Syntax: !talos.random_stream

RangedPackedArrayType¶

Syntax:

!talos.ranged_packed_array<
  ::mlir::Type,   # elementType
  int64_t,   # left
  int64_t   # right
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`
left	`int64_t`
right	`int64_t`

RangedUnpackedArrayType¶

Syntax:

!talos.ranged_unpacked_array<
  ::mlir::Type,   # elementType
  int64_t,   # left
  int64_t   # right
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`
left	`int64_t`
right	`int64_t`

RealType¶

Source-semantic SystemVerilog real

Syntax: !talos.real

RealtimeType¶

Source-semantic SystemVerilog realtime

Syntax: !talos.realtime

RefType¶

Mutable variable or object-field reference

Syntax:

!talos.ref<
  ::mlir::Type   # elementType
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`

ScanStateType¶

State of an active fscanf or sscanf conversion

Syntax: !talos.scan_state

SemaphoreType¶

SystemVerilog semaphore handle

Syntax: !talos.semaphore

SequenceType¶

Syntax: !talos.sequence

ShortRealType¶

Source-semantic SystemVerilog shortreal

Syntax: !talos.shortreal

SourceAggregateType¶

Syntax:

!talos.source_aggregate<
  ::mlir::StringAttr,   # name
  bool,   # isPacked
  bool,   # isUnion
  bool,   # isTagged
  bool,   # isSigned
  bool,   # isFourState
  bool,   # isSoft
  uint64_t,   # bitWidth
  uint64_t,   # selectableWidth
  uint64_t,   # bitstreamWidth
  uint32_t,   # tagBits
  ::mlir::ArrayAttr   # fields
>

Parameters:¶

Parameter	C++ type	Description
name	`::mlir::StringAttr`
isPacked	`bool`
isUnion	`bool`
isTagged	`bool`
isSigned	`bool`
isFourState	`bool`
isSoft	`bool`
bitWidth	`uint64_t`
selectableWidth	`uint64_t`
bitstreamWidth	`uint64_t`
tagBits	`uint32_t`
fields	`::mlir::ArrayAttr`

SourceRangeType¶

Syntax:

!talos.source_range<
  ::mlir::StringAttr,   # startFile
  uint32_t,   # startLine
  uint32_t,   # startColumn
  ::mlir::StringAttr,   # endFile
  uint32_t,   # endLine
  uint32_t,   # endColumn
  ::mlir::StringAttr   # macroName
>

Parameters:¶

Parameter	C++ type	Description
startFile	`::mlir::StringAttr`
startLine	`uint32_t`
startColumn	`uint32_t`
endFile	`::mlir::StringAttr`
endLine	`uint32_t`
endColumn	`uint32_t`
macroName	`::mlir::StringAttr`

StringType¶

Source-semantic SystemVerilog string

Syntax: !talos.string

SubroutineType¶

Syntax:

!talos.subroutine<
  ::mlir::Type,   # signature
  bool   # isTask
>

Parameters:¶

Parameter	C++ type	Description
signature	`::mlir::Type`
isTask	`bool`

TimeType¶

Scaled simulation time

Syntax: !talos.time

TypeReferenceType¶

Syntax: !talos.type_reference

UnboundedType¶

Syntax: !talos.unbounded

UnpackedArrayType¶

Fixed-size unpacked SystemVerilog array

Syntax:

!talos.unpacked_array<
  ::mlir::Type,   # elementType
  unsigned   # size
>

Parameters:¶

Parameter	C++ type	Description
elementType	`::mlir::Type`
size	`unsigned`

UnpackedStructType¶

Unpacked SystemVerilog struct

Syntax:

!talos.unpacked_struct<
  ::mlir::DictionaryAttr   # fields
>

Parameters:¶

Parameter	C++ type	Description
fields	`::mlir::DictionaryAttr`

UnpackedUnionType¶

Unpacked SystemVerilog union

Syntax:

!talos.unpacked_union<
  ::mlir::DictionaryAttr   # fields
>

Parameters:¶

Parameter	C++ type	Description
fields	`::mlir::DictionaryAttr`

UntypedType¶

Syntax: !talos.untyped

VPIHandleType¶

Opaque VPI object handle

Syntax: !talos.vpi_handle

VirtualInterfaceType¶

Syntax:

!talos.virtual_interface<
  ::mlir::SymbolRefAttr,   # interfaceName
  ::mlir::StringAttr   # modport
>

Parameters:¶

Parameter	C++ type	Description
interfaceName	`::mlir::SymbolRefAttr`
modport	`::mlir::StringAttr`

VoidType¶

Source-level SystemVerilog void

Syntax: !talos.void

Enums¶

ArrayCmpPredicate¶

Unpacked array comparison predicate

Cases:¶

Symbol	Value	String
Eq	`0`	eq
Ne	`1`	ne

DPIArgDirection¶

DPI argument direction

Cases:¶

Symbol	Value	String
In	`0`	in
Out	`1`	out
InOut	`2`	inout
Return	`3`	return

DeferAssert¶

Assertion deferral

Cases:¶

Symbol	Value	String
Immediate	`0`	immediate
Observed	`1`	observed
Final	`2`	final

EdgeKind¶

SystemVerilog event edge

Cases:¶

Symbol	Value	String
Change	`0`	change
Posedge	`1`	posedge
Negedge	`2`	negedge
Both	`3`	both

EventRegion¶

IEEE 1800 event region

Cases:¶

Symbol	Value	String
Preponed	`0`	preponed
PreActive	`1`	pre_active
Active	`2`	active
Inactive	`3`	inactive
PreNBA	`4`	pre_nba
NBA	`5`	nba
PostNBA	`6`	post_nba
PreObserved	`7`	pre_observed
Observed	`8`	observed
PostObserved	`9`	post_observed
Reactive	`10`	reactive
ReInactive	`11`	re_inactive
PreReNBA	`12`	pre_re_nba
ReNBA	`13`	re_nba
PostReNBA	`14`	post_re_nba
PrePostponed	`15`	pre_postponed
Postponed	`16`	postponed

FileOpenMode¶

SV file open mode

Cases:¶

Symbol	Value	String
Read	`0`	read
Write	`1`	write
Append	`2`	append
ReadUpdate	`3`	read_update
WriteUpdate	`4`	write_update
AppendUpdate	`5`	append_update

IntegerAlignment¶

Formatted integer alignment

Cases:¶

Symbol	Value	String
Right	`0`	right
Left	`1`	left

IntegerFormat¶

Integer format radix

Cases:¶

Symbol	Value	String
Decimal	`0`	decimal
Binary	`1`	binary
Octal	`2`	octal
HexLower	`3`	hex_lower
HexUpper	`4`	hex_upper

IntegerPadding¶

Formatted integer padding

Cases:¶

Symbol	Value	String
Space	`0`	space
Zero	`1`	zero

JoinKind¶

Fork/join completion policy

Cases:¶

Symbol	Value	String
All	`0`	all
Any	`1`	any
None	`2`	none

LogicBinaryKind¶

Four-state binary operator

Cases:¶

Symbol	Value	String
Add	`0`	add
Sub	`1`	sub
Mul	`2`	mul
Div	`3`	div
Mod	`4`	mod
Pow	`5`	pow
BitAnd	`6`	bit_and
BitOr	`7`	bit_or
BitXor	`8`	bit_xor
BitXnor	`9`	bit_xnor
LogicalAnd	`10`	logical_and
LogicalOr	`11`	logical_or
ShiftLeft	`12`	shift_left
ShiftRight	`13`	shift_right
AShiftRight	`14`	ashift_right
UDiv	`15`	udiv
SDiv	`16`	sdiv
UMod	`17`	umod
SMod	`18`	smod
UPow	`19`	upow
SPow	`20`	spow

LogicCompareKind¶

Four-state comparison operator

Cases:¶

Symbol	Value	String
LogicalEq	`0`	logical_eq
LogicalNe	`1`	logical_ne
CaseEq	`2`	case_eq
CaseNe	`3`	case_ne
WildEq	`4`	wild_eq
WildNe	`5`	wild_ne
Lt	`6`	lt
Le	`7`	le
Gt	`8`	gt
Ge	`9`	ge
ULT	`10`	ult
ULE	`11`	ule
UGT	`12`	ugt
UGE	`13`	uge
SLT	`14`	slt
SLE	`15`	sle
SGT	`16`	sgt
SGE	`17`	sge
CaseZEq	`18`	casez_eq
CaseXZEq	`19`	casexz_eq

LogicReduceKind¶

Four-state reduction operator

Cases:¶

Symbol	Value	String
And	`0`	and
Or	`1`	or
Xor	`2`	xor
Nand	`3`	nand
Nor	`4`	nor
Xnor	`5`	xnor

LogicUnaryKind¶

Four-state unary operator

Cases:¶

Symbol	Value	String
Plus	`0`	plus
Negate	`1`	negate
BitNot	`2`	bit_not
LogicalNot	`3`	logical_not

NetKind¶

Net resolution function

Cases:¶

Symbol	Value	String
Wire	`0`	wire
Tri	`1`	tri
Wand	`2`	wand
Wor	`3`	wor
TriAnd	`4`	triand
TriOr	`5`	trior
Tri0	`6`	tri0
Tri1	`7`	tri1
Supply0	`8`	supply0
Supply1	`9`	supply1
TriReg	`10`	trireg
UWire	`11`	uwire
Interconnect	`12`	interconnect
UserDefined	`13`	user_defined
Unknown	`14`	unknown

ProcessKind¶

Simulation process kind

Cases:¶

Symbol	Value	String
Initial	`0`	initial
Always	`1`	always
AlwaysComb	`2`	always_comb
AlwaysFF	`3`	always_ff
AlwaysLatch	`4`	always_latch
Final	`5`	final
Task	`6`	task
Fork	`7`	fork

RealFormat¶

Real number format

Cases:¶

Symbol	Value	String
Float	`0`	float
Exponential	`1`	exponential
General	`2`	general

Severity¶

Diagnostic severity

Cases:¶

Symbol	Value	String
Info	`0`	info
Warning	`1`	warning
Error	`2`	error
Fatal	`3`	fatal

StringCmpPredicate¶

Dynamic string comparison predicate

Cases:¶

Symbol	Value	String
Eq	`0`	eq
Ne	`1`	ne
Lt	`2`	lt
Le	`3`	le
Gt	`4`	gt
Ge	`5`	ge

SVArgumentDirection¶

SystemVerilog port or argument direction

Cases:¶

Symbol	Value	String
In	`0`	in
Out	`1`	out
InOut	`2`	inout
Ref	`3`	ref

SVAssertionAbortAction¶

Accept or reject property abort action

Cases:¶

Symbol	Value	String
Accept	`0`	accept
Reject	`1`	reject

SVAssertionBinaryOperator¶

SystemVerilog binary sequence or property operator

Cases:¶

Symbol	Value	String
And	`0`	and
Or	`1`	or
Intersect	`2`	intersect
Throughout	`3`	throughout
Within	`4`	within
Iff	`5`	iff
Until	`6`	until
SUntil	`7`	s_until
UntilWith	`8`	until_with
SUntilWith	`9`	s_until_with
Implies	`10`	implies
OverlappedImplication	`11`	overlapped_implication
NonOverlappedImplication	`12`	nonoverlapped_implication
OverlappedFollowedBy	`13`	overlapped_followed_by
NonOverlappedFollowedBy	`14`	nonoverlapped_followed_by

SVAssertionKind¶

Immediate or concurrent assertion directive kind

Cases:¶

Symbol	Value	String
Assert	`0`	assert
Assume	`1`	assume
CoverProperty	`2`	cover_property
CoverSequence	`3`	cover_sequence
Restrict	`4`	restrict
Expect	`5`	expect

SVAssertionStrength¶

Strong or weak property qualification

Cases:¶

Symbol	Value	String
Strong	`0`	strong
Weak	`1`	weak

SVAssertionUnaryOperator¶

SystemVerilog unary sequence or property operator

Cases:¶

Symbol	Value	String
Not	`0`	not
NextTime	`1`	nexttime
SNextTime	`2`	s_nexttime
Always	`3`	always
SAlways	`4`	s_always
Eventually	`5`	eventually
SEventually	`6`	s_eventually

SVAssignmentKind¶

SystemVerilog assignment scheduling kind

Cases:¶

Symbol	Value	String
Blocking	`0`	blocking
Nonblocking	`1`	nonblocking

SVBinaryOperator¶

Complete source-level SystemVerilog binary operator

Cases:¶

Symbol	Value	String
Add	`0`	add
Subtract	`1`	subtract
Multiply	`2`	multiply
Divide	`3`	divide
Mod	`4`	mod
BinaryAnd	`5`	binary_and
BinaryOr	`6`	binary_or
BinaryXor	`7`	binary_xor
BinaryXnor	`8`	binary_xnor
Equality	`9`	equality
Inequality	`10`	inequality
CaseEquality	`11`	case_equality
CaseInequality	`12`	case_inequality
GreaterThanEqual	`13`	greater_than_equal
GreaterThan	`14`	greater_than
LessThanEqual	`15`	less_than_equal
LessThan	`16`	less_than
WildcardEquality	`17`	wildcard_equality
WildcardInequality	`18`	wildcard_inequality
LogicalAnd	`19`	logical_and
LogicalOr	`20`	logical_or
LogicalImplication	`21`	logical_implication
LogicalEquivalence	`22`	logical_equivalence
LogicalShiftLeft	`23`	logical_shift_left
LogicalShiftRight	`24`	logical_shift_right
ArithmeticShiftLeft	`25`	arithmetic_shift_left
ArithmeticShiftRight	`26`	arithmetic_shift_right
Power	`27`	power

SVCaseCondition¶

SystemVerilog case matching mode

Cases:¶

Symbol	Value	String
Normal	`0`	normal
WildcardXOrZ	`1`	wildcard_x_or_z
WildcardJustZ	`2`	wildcard_just_z
Inside	`3`	inside

SVChargeStrength¶

SystemVerilog trireg charge strength

Cases:¶

Symbol	Value	String
Small	`0`	small
Medium	`1`	medium
Large	`2`	large

SVCoverageBinChildRole¶

Semantic role of a direct coverage-bin child

Cases:¶

Symbol	Value	String
Iff	`0`	iff
NumberOfBins	`1`	number_of_bins
SetCoverage	`2`	set_coverage
With	`3`	with
CrossSelect	`4`	cross_select
Value	`5`	value
TransitionItem	`6`	transition_item
TransitionRepeatFrom	`7`	transition_repeat_from
TransitionRepeatTo	`8`	transition_repeat_to

SVCoverageBinKind¶

Coverage bin classification

Cases:¶

Symbol	Value	String
Bins	`0`	bins
IllegalBins	`1`	illegal_bins
IgnoreBins	`2`	ignore_bins

SVCoverageBlockEventKind¶

Begin or end block sampling event

Cases:¶

Symbol	Value	String
Begin	`0`	begin
End	`1`	end

SVCoverageEventKind¶

Declared covergroup sampling form

Cases:¶

Symbol	Value	String
None	`0`	none
Clocking	`1`	clocking
CustomSample	`2`	custom_sample
Block	`3`	block
Inherited	`4`	inherited

SVCoverageExpressionRole¶

Semantic role of a coverpoint or cross expression child

Cases:¶

Symbol	Value	String
Sample	`0`	sample
Iff	`1`	iff

SVCoverageOptionKind¶

Standard coverage option identity

Cases:¶

Symbol	Value	String
Name	`0`	name
Weight	`1`	weight
Goal	`2`	goal
Comment	`3`	comment
AtLeast	`4`	at_least
AutoBinMax	`5`	auto_bin_max
CrossNumPrintMissing	`6`	cross_num_print_missing
CrossRetainAutoBins	`7`	cross_retain_auto_bins
DetectOverlap	`8`	detect_overlap
PerInstance	`9`	per_instance
GetInstCoverage	`10`	get_inst_coverage
Strobe	`11`	strobe
MergeInstances	`12`	merge_instances
DistributeFirst	`13`	distribute_first
RealInterval	`14`	real_interval

SVCoverageOptionOwnerKind¶

Coverage construct that owns a definition-time option setter

Cases:¶

Symbol	Value	String
Covergroup	`0`	covergroup
Coverpoint	`1`	coverpoint
Cross	`2`	cross

SVCoverageOptionScopeKind¶

Instance option or covergroup type option

Cases:¶

Symbol	Value	String
Instance	`0`	instance
Type	`1`	type

SVCoverageSelectBinaryOperator¶

Binary coverage-bin selection operator

Cases:¶

Symbol	Value	String
And	`0`	and
Or	`1`	or

SVCoverageSelectUnaryOperator¶

Unary coverage-bin selection operator

Cases:¶

Symbol	Value	String
Negation	`0`	negation

SVCoverageTransitionRepeatKind¶

Coverage transition repetition kind

Cases:¶

Symbol	Value	String
None	`0`	none
Consecutive	`1`	consecutive
Nonconsecutive	`2`	nonconsecutive
GoTo	`3`	goto

SVDefinitionKind¶

SystemVerilog design-unit definition kind

Cases:¶

Symbol	Value	String
Module	`0`	module
Interface	`1`	interface
Program	`2`	program

SVDriveStrength¶

SystemVerilog drive strength for one logic polarity

Cases:¶

Symbol	Value	String
Supply	`0`	supply
Strong	`1`	strong
Pull	`2`	pull
Weak	`3`	weak
HighZ	`4`	highz

SVDynamicCastKind¶

Elaborated SystemVerilog dynamic-cast behavior

Cases:¶

Symbol	Value	String
AlwaysSuccess	`0`	always_success
AlwaysFail	`1`	always_fail
EnumMembership	`2`	enum_membership
ClassRuntime	`3`	class_runtime

SVIntegralFlavor¶

Declared SystemVerilog integral spelling

Cases:¶

Symbol	Value	String
Generic	`0`	generic
Bit	`1`	bit
Logic	`2`	logic
Reg	`3`	reg
ShortInt	`4`	shortint
Int	`5`	int
LongInt	`6`	longint
Byte	`7`	byte
Integer	`8`	integer
Time	`9`	time

SVNetExpansionHint¶

Explicit SystemVerilog net vector expansion request

Cases:¶

Symbol	Value	String
None	`0`	none
Vectored	`1`	vectored
Scalared	`2`	scalared

SVNetKind¶

SystemVerilog net resolution kind

Cases:¶

Symbol	Value	String
Unknown	`0`	unknown
Wire	`1`	wire
WAnd	`2`	wand
WOr	`3`	wor
Tri	`4`	tri
TriAnd	`5`	triand
TriOr	`6`	trior
Tri0	`7`	tri0
Tri1	`8`	tri1
TriReg	`9`	trireg
Supply0	`10`	supply0
Supply1	`11`	supply1
UWire	`12`	uwire
Interconnect	`13`	interconnect
UserDefined	`14`	user_defined

SVPortConnectionKind¶

Elaborated port association provenance

Cases:¶

Symbol	Value	String
Ordered	`0`	ordered
Named	`1`	named
Implicit	`2`	implicit
Wildcard	`3`	wildcard
Omitted	`4`	omitted
ExplicitOpen	`5`	explicit_open
Default	`6`	default

SVProceduralBlockKind¶

SystemVerilog procedural block kind

Cases:¶

Symbol	Value	String
Initial	`0`	initial
Final	`1`	final
Always	`2`	always
AlwaysComb	`3`	always_comb
AlwaysLatch	`4`	always_latch
AlwaysFF	`5`	always_ff

SVRandMode¶

SystemVerilog randomization mode

Cases:¶

Symbol	Value	String
None	`0`	none
Rand	`1`	rand
RandC	`2`	randc

SVRangeSelectionKind¶

SystemVerilog packed range selection kind

Cases:¶

Symbol	Value	String
Simple	`0`	simple
IndexedUp	`1`	indexed_up
IndexedDown	`2`	indexed_down

SVSequenceRepetitionKind¶

SystemVerilog sequence repetition kind

Cases:¶

Symbol	Value	String
Consecutive	`0`	consecutive
Nonconsecutive	`1`	nonconsecutive
GoTo	`2`	goto

SVStatementBlockKind¶

SystemVerilog sequential or parallel statement block kind

Cases:¶

Symbol	Value	String
Sequential	`0`	sequential
JoinAll	`1`	join_all
JoinAny	`2`	join_any
JoinNone	`3`	join_none

SVSubroutineKind¶

SystemVerilog function or task kind

Cases:¶

Symbol	Value	String
Function	`0`	function
Task	`1`	task

SVUnaryOperator¶

Complete source-level SystemVerilog unary operator

Cases:¶

Symbol	Value	String
Plus	`0`	plus
Minus	`1`	minus
BitwiseNot	`2`	bitwise_not
BitwiseAnd	`3`	bitwise_and
BitwiseOr	`4`	bitwise_or
BitwiseXor	`5`	bitwise_xor
BitwiseNand	`6`	bitwise_nand
BitwiseNor	`7`	bitwise_nor
BitwiseXnor	`8`	bitwise_xnor
LogicalNot	`9`	logical_not
Preincrement	`10`	preincrement
Predecrement	`11`	predecrement
Postincrement	`12`	postincrement
Postdecrement	`13`	postdecrement

SVUniquePriorityCheck¶

Unique or priority runtime check

Cases:¶

Symbol	Value	String
None	`0`	none
Unique	`1`	unique
Unique0	`2`	unique0
Priority	`3`	priority

SVValueRangeKind¶

Kind of membership value range

Cases:¶

Symbol	Value	String
Simple	`0`	simple
AbsoluteTolerance	`1`	absolute_tolerance
RelativeTolerance	`2`	relative_tolerance

SVVariableLifetime¶

SystemVerilog variable storage lifetime

Cases:¶

Symbol	Value	String
Automatic	`0`	automatic
Static	`1`	static

SVVisibility¶

SystemVerilog class member visibility

Cases:¶

Symbol	Value	String
Public	`0`	public
Protected	`1`	protected
Local	`2`	local

‘talos’ Dialect¶

Operations¶

talos.assert.immediate (::talos::ir::AssertImmediateOp)¶

Attributes:¶

Operands:¶

talos.assert.sample (::talos::ir::AssertSampleOp)¶

Attributes:¶

Operands:¶

talos.assoc.create (::talos::ir::AssocCreateOp)¶

Results:¶

talos.assoc.delete (::talos::ir::AssocDeleteOp)¶

Operands:¶

talos.assoc.element_ref (::talos::ir::AssocElementRefOp)¶

Operands:¶

Results:¶

talos.assoc.exists (::talos::ir::AssocExistsOp)¶

Operands:¶

Results:¶

talos.box (::talos::ir::BoxOp)¶

Operands:¶

Results:¶

talos.class (::talos::ir::ClassOp)¶

Attributes:¶

talos.class.end (::talos::ir::ClassEndOp)¶

talos.class.field (::talos::ir::ClassFieldOp)¶

Attributes:¶

talos.class.method (::talos::ir::ClassMethodOp)¶

Attributes:¶

talos.class.method_return (::talos::ir::ClassMethodReturnOp)¶

Operands:¶

talos.constraint.end (::talos::ir::ConstraintEndOp)¶

talos.constraint.get (::talos::ir::ConstraintGetOp)¶

Attributes:¶

Results:¶

talos.constraint.require (::talos::ir::ConstraintRequireOp)¶

Operands:¶

talos.constraint.set (::talos::ir::ConstraintSetOp)¶

Attributes:¶

talos.cover.sample (::talos::ir::CoverSampleOp)¶

Attributes:¶

Operands:¶

talos.diagnostic (::talos::ir::DiagnosticOp)¶

Attributes:¶

Operands:¶

talos.dpi.task_call (::talos::ir::DPITaskCallOp)¶

Attributes:¶

Operands:¶

Results:¶

talos.dynarray.create (::talos::ir::DynArrayCreateOp)¶

Operands:¶

Results:¶

talos.dynarray.element_ref (::talos::ir::DynArrayElementRefOp)¶

Operands:¶

Results:¶

talos.dynarray.resize (::talos::ir::DynArrayResizeOp)¶

Operands:¶

talos.dynarray.size (::talos::ir::DynArraySizeOp)¶

Operands:¶

Results:¶

talos.event.create (::talos::ir::EventCreateOp)¶

Results:¶

talos.event.trigger (::talos::ir::EventTriggerOp)¶

Attributes:¶

Operands:¶

talos.finish (::talos::ir::FinishOp)¶

Attributes:¶

talos.force (::talos::ir::ForceOp)¶

Operands:¶

talos.get_global (::talos::ir::GetGlobalOp)¶

Attributes:¶

Results:¶

talos.global (::talos::ir::GlobalOp)¶

Attributes:¶

talos.global.return (::talos::ir::GlobalReturnOp)¶

Operands:¶

talos.load (::talos::ir::LoadOp)¶

Operands:¶

Results:¶

talos.logic.binary (::talos::ir::LogicBinaryOp)¶

Attributes:¶

`talos.assert.immediate` (::talos::ir::AssertImmediateOp)¶

`talos.assert.sample` (::talos::ir::AssertSampleOp)¶

`talos.assoc.create` (::talos::ir::AssocCreateOp)¶

`talos.assoc.delete` (::talos::ir::AssocDeleteOp)¶

`talos.assoc.element_ref` (::talos::ir::AssocElementRefOp)¶

`talos.assoc.exists` (::talos::ir::AssocExistsOp)¶

`talos.box` (::talos::ir::BoxOp)¶

`talos.class` (::talos::ir::ClassOp)¶

`talos.class.end` (::talos::ir::ClassEndOp)¶

`talos.class.field` (::talos::ir::ClassFieldOp)¶

`talos.class.method` (::talos::ir::ClassMethodOp)¶

`talos.class.method_return` (::talos::ir::ClassMethodReturnOp)¶

`talos.constraint.end` (::talos::ir::ConstraintEndOp)¶

`talos.constraint.get` (::talos::ir::ConstraintGetOp)¶

`talos.constraint.require` (::talos::ir::ConstraintRequireOp)¶

`talos.constraint.set` (::talos::ir::ConstraintSetOp)¶

`talos.cover.sample` (::talos::ir::CoverSampleOp)¶

`talos.diagnostic` (::talos::ir::DiagnosticOp)¶

`talos.dpi.task_call` (::talos::ir::DPITaskCallOp)¶

`talos.dynarray.create` (::talos::ir::DynArrayCreateOp)¶

`talos.dynarray.element_ref` (::talos::ir::DynArrayElementRefOp)¶

`talos.dynarray.resize` (::talos::ir::DynArrayResizeOp)¶

`talos.dynarray.size` (::talos::ir::DynArraySizeOp)¶

`talos.event.create` (::talos::ir::EventCreateOp)¶

`talos.event.trigger` (::talos::ir::EventTriggerOp)¶

`talos.finish` (::talos::ir::FinishOp)¶

`talos.force` (::talos::ir::ForceOp)¶

`talos.get_global` (::talos::ir::GetGlobalOp)¶

`talos.global` (::talos::ir::GlobalOp)¶

`talos.global.return` (::talos::ir::GlobalReturnOp)¶

`talos.load` (::talos::ir::LoadOp)¶

`talos.logic.binary` (::talos::ir::LogicBinaryOp)¶

`talos.logic.bool_cast` (::talos::ir::LogicBoolCastOp)¶

`talos.logic.compare` (::talos::ir::LogicCompareOp)¶

`talos.logic.concat` (::talos::ir::LogicConcatOp)¶

`talos.logic.constant` (::talos::ir::LogicConstantOp)¶

`talos.logic.dyn_extract` (::talos::ir::LogicDynExtractOp)¶

`talos.logic.extract` (::talos::ir::LogicExtractOp)¶

`talos.logic.from_bits` (::talos::ir::LogicFromBitsOp)¶

`talos.logic.insert` (::talos::ir::LogicInsertOp)¶

`talos.logic.is_known` (::talos::ir::LogicIsKnownOp)¶

`talos.logic.mux` (::talos::ir::LogicMuxOp)¶

`talos.logic.reduce` (::talos::ir::LogicReduceOp)¶

`talos.logic.replicate` (::talos::ir::LogicReplicateOp)¶

`talos.logic.resize` (::talos::ir::LogicResizeOp)¶

`talos.logic.shift` (::talos::ir::LogicShiftOp)¶

`talos.logic.to_bits` (::talos::ir::LogicToBitsOp)¶

`talos.logic.unary` (::talos::ir::LogicUnaryOp)¶

`talos.mailbox.create` (::talos::ir::MailboxCreateOp)¶

`talos.mailbox.get` (::talos::ir::MailboxGetOp)¶

`talos.mailbox.put` (::talos::ir::MailboxPutOp)¶

`talos.mailbox.try_get` (::talos::ir::MailboxTryGetOp)¶

`talos.nba.enqueue` (::talos::ir::NBAEnqueueOp)¶